Sythesis vs. Simulation

M

Mike

Hi

I have some piece of code that should only be used for simulation & not
for sythesis. Is there any way to tell Xilinx XST that it should ignore
some lines of code for mapping the description onto the slices?

THanks
Mike
 
T

Tricky

Hi

I have some piece of code that should only be used for simulation & not
for sythesis. Is there any way to tell Xilinx XST that it should ignore
some lines of code for mapping the description onto the slices?

THanks
Mike

The synthesis or synopsis directives, that are pretty much industry
standard, thus:

--synthesis translate_off
.....
the code you want the synthesiser to ignore goes here
.....
--synthesis translate_on

(Feel free to replace sythesis with synopsis)
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Members online

No members online now.

Forum statistics

Threads
473,744
Messages
2,569,484
Members
44,903
Latest member
orderPeak8CBDGummies

Latest Threads

Top