Sythesis vs. Simulation

Discussion in 'VHDL' started by Mike, Jul 7, 2008.

  1. Mike

    Mike Guest

    Hi

    I have some piece of code that should only be used for simulation & not
    for sythesis. Is there any way to tell Xilinx XST that it should ignore
    some lines of code for mapping the description onto the slices?

    THanks
    Mike
     
    Mike, Jul 7, 2008
    #1
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  2. Mike Treseler, Jul 7, 2008
    #2
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  3. Mike

    Tricky Guest

    On 7 Jul, 21:32, Mike <> wrote:
    > Hi
    >
    > I have some piece of code that should only be used for simulation & not
    > for sythesis. Is there any way to tell Xilinx XST that it should ignore
    > some lines of code for mapping the description onto the slices?
    >
    > THanks
    > Mike


    The synthesis or synopsis directives, that are pretty much industry
    standard, thus:

    --synthesis translate_off
    .....
    the code you want the synthesiser to ignore goes here
    .....
    --synthesis translate_on

    (Feel free to replace sythesis with synopsis)
     
    Tricky, Jul 8, 2008
    #3
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