Task in verilog

[FPGA]

Is task in verilog equivalent to procedure in VHDL? I am trying to
convert a verilog file to vhdl.

Verilog =>
// string data type
reg [8*4:1]a;
reg [8*255:0]b;

VHDL =>
Is the above equivalent to
variable a : string(1 to 8*4)
variable b : string(1 to 8*255)

 

[FPGA]

Is task in verilog equivalent to procedure in VHDL? I am trying to
convert a verilog file to vhdl.

Broadly similar, in the sense that both Verilog tasks and
VHDL procedures...

- have in, out and inout arguments ("parameters" in VHDL)
- can consume time by performing delay or wait-for operations
- can have side-effects (i.e. can read and write variables
  that are not arguments, but are in the enclosing scope)

but there are some important differences, particularly
in the way arguments are passed to and from them.  
Automatic translation is unlikely to succeed in any
but the simplest cases.

Verilog =>
// string data type
reg [8*4:1]a;
reg [8*255:0]b;

VHDL =>
Is the above equivalent to
variable a : string(1 to 8*4)
variable b : string(1 to 8*255)

Lose the "8*" in VHDL and you're about right.
A Verilog string of N characters is represented
in a vector of 8*N bits.  A VHDL string of N
characters is represented in a STRING(1 to N).
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

I would like to check if a:string(1 to 2) = x"1234"

if a = x"1234" then

I get an error that expected size is 2 and actual is 4. String of 2
characters means 16 bits. Why am I getting this error when x"1234" =
16 bits

 

[FPGA]

Broadly similar, in the sense that both Verilog tasks and
VHDL procedures...

- have in, out and inout arguments ("parameters" in VHDL)
- can consume time by performing delay or wait-for operations
- can have side-effects (i.e. can read and write variables
  that are not arguments, but are in the enclosing scope)

but there are some important differences, particularly
in the way arguments are passed to and from them.  
Automatic translation is unlikely to succeed in any
but the simplest cases.

Verilog =>
// string data type
reg [8*4:1]a;
reg [8*255:0]b;
VHDL =>
Is the above equivalent to
variable a : string(1 to 8*4)
variable b : string(1 to 8*255)

Lose the "8*" in VHDL and you're about right.
A Verilog string of N characters is represented
in a vector of 8*N bits.  A VHDL string of N
characters is represented in a STRING(1 to N).

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

I would like to check if a:string(1 to 2) = x"1234"

if a = x"1234" then

I get an error that expected size is 2 and actual is 4. String of 2
characters means 16 bits. Why am I getting this error when x"1234" =
16 bits- Hide quoted text -

- Show quoted text -

type string is array (positive range<>) of character;

 

[FP]

Not in VHDL it doesn't.  I did warn you that automatic
translation would fail.  in VHDL a string of 2 characters
is precisely that, an array of two CHARACTERS, and only in
your hardware mindset is that exactly the same as 16 bits.

You'll need either an overloaded equality test operator
or a type conversion function.  This would work, if
I understand your intent correctly:

  function to_std_logic_vector (s: string)
    return std_logic_vector
      is
    variable v: std_logic_vector (1 to 8*s'length+7);
  begin
    for i in s'range loop
      v(8*i to 8*i+7) :=
            std_logic_vector(to_unsigned(s(i)'pos, 8));
    end loop;
    return v;
  end;

Now you could do

  if to_std_logic_vector(a) = x"1234" then ...

And perhaps, if you really need convenient comparison,

  function "=" (L: string, R: std_logic_vector) return boolean is
  begin
    return to_std_logic_vector(L) = R;
  end;

and then you can do

  if a = x"1234" then ...

Good luck.  VHDL is not Verilog.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Thanks a lot Jonathan. You suggestions are appreciated.

 

[sky465nm]

Is task in verilog equivalent to procedure in VHDL? I am trying to
convert a verilog file to vhdl.

Verilog =>
// string data type
reg [8*4:1]a;
reg [8*255:0]b;

VHDL =>
Is the above equivalent to
variable a : string(1 to 8*4)
variable b : string(1 to 8*255)

Just a thought..:
variable b : string(0 to 8*255)

 

[Tricky]

Just a thought..:
variable b : string(0 to 8*255)

Unfortunatly not. String has a range that uses positive instead of
integer, so must always be 1 to somthing. You cant use downto either.