TCL testcase in Modelsim.

Discussion in 'VHDL' started by bigyellow, Feb 18, 2008.

  1. bigyellow

    bigyellow Guest

    Hello,

    Does anybody have experience on writing TCL testcase in Modelsim? I
    only have VHDL simulation license of Modelsim, I used to write both
    testbench and testcase in VHDL. But I feel VHDL is not that nice to
    implement testcase.

    So I am thinking to implement my testbench in VHDL, and write the
    testcases in TCL for my next project. Of course the verification
    should be self-checking.

    Does it sounds feasible? How is the simulation speed? Can anyone give
    me some reference? Thanks in advance.

    -Best Regards
    Jim
    bigyellow, Feb 18, 2008
    #1
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  2. bigyellow wrote:

    > Does anybody have experience on writing TCL testcase in Modelsim? I
    > only have VHDL simulation license of Modelsim, I used to write both
    > testbench and testcase in VHDL. But I feel VHDL is not that nice to
    > implement testcase.


    I would consider a testcase to be a subset of a testbench.
    I would also consider vhdl to be 'nicer' than TCL for this purpose.
    See http://home.comcast.net/~mike_treseler/test_uart.vhd

    -- Mike Treseler
    Mike Treseler, Feb 18, 2008
    #2
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  3. bigyellow

    bigyellow Guest

    Yes, I also did the same thing. Wrote hundreds of procedures and then
    use them in different testcases.
    I think it is quite complicate. For example, I need logics, procedures
    etc to control the behavior of testbenchs, but in modelsim, I can do
    it by forcing the register's value directly, rather than use vhdl
    procedure to write the register.

    I am starter of tcl, and I just wonder to know if using TCL could
    simplify the verification process.

    -Jim

    On Feb 18, 10:46 pm, Mike Treseler <> wrote:
    > bigyellow wrote:
    > > Does anybody have experience on writing TCL testcase in Modelsim? I
    > > only have VHDL simulation license of Modelsim, I used to write both
    > > testbench and testcase in VHDL. But I feel VHDL is not that nice to
    > > implement testcase.

    >
    > I would consider a testcase to be a subset of a testbench.
    > I would also consider vhdl to be 'nicer' than TCL for this purpose.
    > Seehttp://home.comcast.net/~mike_treseler/test_uart.vhd
    >
    > -- Mike Treseler
    bigyellow, Feb 18, 2008
    #3
  4. bigyellow wrote:
    > Yes, I also did the same thing. Wrote hundreds of procedures and then
    > use them in different testcases.
    > I think it is quite complicate. For example, I need logics, procedures
    > etc to control the behavior of testbenchs, but in modelsim, I can do
    > it by forcing the register's value directly, rather than use vhdl
    > procedure to write the register.


    Once I have virtualized a register load with a vhdl procedure,
    calling this procedure is no more difficult than a tcl force command.
    It also matches what the firmware has to do.
    If vhdl can't cover a verification, neither can the system software.

    > I am starter of tcl, and I just wonder to know if using TCL could
    > simplify the verification process.


    TCL is well suited to orchestrate multiple OS commands and vsim runs
    if python or sh is not available. I would not use it directly
    for bit level stimulus or verification, but some do.

    -- Mike Treseler
    Mike Treseler, Feb 18, 2008
    #4
  5. I have done a lot of work with TCL. If you do not already know TCL, I
    suggest you stay with VHDL testbenches. The TCL code will not buy you
    anything more than automating some tool commands. Which will not be
    portable to other tools.

    If you write your Testbench in VHDL your employer can change tool vedors
    with a small amount of changes needed for coding style. If your testbenches
    are written in TCL, then then every testbench will have to be modified if
    your tool vendor changes.

    I have written test benches in TCL, VHDL, Verilog and System Verilog. It is
    better to stick with one language and work with what you know. If you are
    set on using TCL for verification, check out "Practical Programming in TCL
    and TK", Brent B. Welch.
    This book will give you a firm foundation in TCL programming. NOTE: Not all
    TCL features are supported by tool vendors, even if thier input environment
    is based on TCL.

    Simulation speed depends on how the original tool handled the VHDL
    testbench.
    In general the TCL is going to be slower. IF you need a faster Testbecnh.
    Look into System C.


    "bigyellow" <> wrote in message
    news:...
    > Hello,
    >
    > Does anybody have experience on writing TCL testcase in Modelsim? I
    > only have VHDL simulation license of Modelsim, I used to write both
    > testbench and testcase in VHDL. But I feel VHDL is not that nice to
    > implement testcase.
    >
    > So I am thinking to implement my testbench in VHDL, and write the
    > testcases in TCL for my next project. Of course the verification
    > should be self-checking.
    >
    > Does it sounds feasible? How is the simulation speed? Can anyone give
    > me some reference? Thanks in advance.
    >
    > -Best Regards
    > Jim
    Dwayne Dilbeck, Feb 19, 2008
    #5
  6. bigyellow wrote:

    > Hello,
    >
    > Does anybody have experience on writing TCL testcase in Modelsim? I
    > only have VHDL simulation license of Modelsim, I used to write both
    > testbench and testcase in VHDL. But I feel VHDL is not that nice to
    > implement testcase.


    Then you should get to know VHDL better. VHDL offers a lot of high level
    constructs and ways to write behavioral code. If you come from an RTL back
    ground, then the hardest thing I suppose is switching to a behavioral mind
    set. You are freed from all limitations otherwise imposed to you by the
    synthesizer.

    > So I am thinking to implement my testbench in VHDL, and write the
    > testcases in TCL for my next project.


    I would not go into that path. As others already said: it is not portable.
    And VHDL offers much more than Tcl.

    --
    Paul Uiterlinden
    www.aimvalley.nl
    e-mail addres: remove the not.
    Paul Uiterlinden, Feb 21, 2008
    #6
  7. Dwayne Dilbeck wrote:

    > Simulation speed depends on how the original tool handled the VHDL
    > testbench.
    > In general the TCL is going to be slower. IF you need a faster Testbecnh.
    > Look into System C.


    But in general a VHDL testbench is not limiting the simulation speed, the
    design is. The testbench is written in a behavioral way, which simulates
    much faster than the RTL code of the design.

    --
    Paul Uiterlinden
    www.aimvalley.nl
    e-mail addres: remove the not.
    Paul Uiterlinden, Feb 21, 2008
    #7
  8. bigyellow

    Guest

    On Feb 18, 5:20 pm, bigyellow <> wrote:
    > Hello,
    >
    > Does anybody have experience on writing TCL testcase in Modelsim? I
    > only have VHDL simulation license of Modelsim, I used to write both
    > testbench and testcase in VHDL. But I feel VHDL is not that nice to
    > implement testcase.
    >
    > So I am thinking to implement my testbench in VHDL, and write the
    > testcases in TCL for my next project. Of course the verification
    > should be self-checking.
    >
    > Does it sounds feasible? How is the simulation speed?  Can anyone give
    > me some reference?  Thanks in advance.
    >
    > -Best Regards
    > Jim


    Dear Jim,

    Have you solve the problem? I also had such idea.
    Our method is like yours. Testbench written in VHDL (I am using System
    Verilog now), and the test case are text based command. I want to add
    TCL script in the test case.

    I think we are using an advanced method in the simulation
    (verifiation). Hope we can keep touch.

    My email addres :

    Thanks

    Jeffery
    , Mar 29, 2008
    #8
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