Test bench for a counter for vga hsync and vsync

[snjsteve]

i keep compiling my testbench and it tells me
( Prelab1_TB.vhd(34): Signal "t_clk" is type ieee.std_logic_1164.std_logic; expecting type ieee.std_logic_1164.std_logic_vector.), and
(Prelab1_TB.vhd(34): Signal "t_vcount" is type ieee.std_logic_1164.std_logic_vector; expecting type ieee.std_logic_1164.std_logic.)

even though the clk is one 1 bit and t_vcount is 10 bits.

Here's my code for the testbench

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity Prelab1_tb is
end Prelab1_tb;

architecture TB of Prelab1_tb is

component VGA_sync_gen is
PORT(

clk : IN STD_LOGIC;
Hcount : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
Vcount : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
Horiz_Sync : OUT STD_LOGIC;
Vert_Sync : OUT STD_LOGIC;
Viden : OUT STD_LOGIC);

end component;

signal T_clk : std_logic := '0';
signal T_Hcount : STD_LOGIC_VECTOR(9 DOWNTO 0);
signal T_Vcount : STD_LOGIC_VECTOR(9 DOWNTO 0);
signal T_Hor : std_logic;
signal T_Ver : std_logic;
signal T_Video : std_logic;
signal sim_done : std_logic ;

begin

UUT : entity work.VGA_sync_gen
line 34------------>port map (T_clk ,T_Hcount,T_Vcount,T_Hor,T_Ver,T_Video );


process
begin
T_clk <= '0';
wait for 10 ns;
T_clk <= '1';
wait for 10 ns;
end process;

process
begin
If ((T_Hcount = 799) and (T_Vcount = 525)) then
sim_done <= '1';
report "SIMULATION FINISHED!";
else
sim_done <= '0';
End if;

end process;
end TB;