test bench

[craigs2]

chaps i have written the following code for a 16x12 RAM, but i now need to write a test bench, does anybody have anything i could use?

entity RAM16x12 is
port (address: in integer range 0 to 15;
Data: inout std_ulogic_vector(11 downto 0);
CS, WE, OE: in std_ulogic);
end entity RAM16x12;

architecture RTL of RAM16x12 is
begin
p0: process (address, CS, WE, OE) is
type ram_array is array (0 to 15) of
std_ulogic_vector(11 downto 0);
variable mem: ram_array;
begin
Data <= (others => 'Z');
if CS = '0' then
if OE = '0' then
Data <= mem(address);
elsif WE = '0' then
mem(address) := Data;
end if;
end if;
end process p0;
end architecture RTL;

thanks in advance

s