test bench

Discussion in 'VHDL' started by predador, May 24, 2008.

  1. predador

    predador

    Joined:
    May 24, 2008
    Messages:
    1
    i need to write an test bench for this waveforms
    [​IMG]

    for now i hav writed this:
    can somebody give me tips concerning this code
    I am with problems for the A entrance that seems to be one clock and for the exit Y which i have no idea what will be

    perhaps it can use this for the A
    predador, May 24, 2008
    #1
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