test-bench

[Amit]

hello,

in a vhdl testbench (just learning) I saw a piece of code as:

w_reset <= '0', '1' after 40ns, '0' after 60ns;

so far what I have seen is only 1 value assignment .What about this
case?


any help is appreciated.

 

[jeppe]

well the easiest way to learn more about this topics will be the interactive book on VHDL - EVITA. Can be found at the net and downloaded (free)

Jeppe

 

[Amit]

This kind of signal assignment is known as a "waveform" in
VHDL.  It does pretty much what you might expect: drive
w_reset to 0 immediately, drive it to 1 at now+40ns,
drive it to 0 at now+60ns.  So you get a 20ns pulse on
w_reset, lasting from 40ns to 60ns.  You can specify
as many transitions as you want in the waveform, but
they must be in ascending order of time.

Like any signal assignment, you can use this in the
procedural code in a process or you can write it
stand-alone in the architecture body as a concurrent
signal assignment.  Within a process it is done
at the moment the flow of execution reaches that
statement.  The future assignments are scheduled,
and then process execution continues with no delay.
If you write it as a concurrent signal assignment
it acts as a process on its own, and therefore
executes just once at time 0.

You can play silly games with concurrent signal
assignment to make clock generators:

  signal clock: std_logic := '0';
  ...
  clock <= not clock after 5 ns;

But that is fairly hard to understand and I
don't really like it.  The best use for
a concurrent signal assignment with a waveform
is the one you showed: a one-shot pulse generator.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Hello Jonathan,

Thank you for help me to understand how it works. Just one question:

You said:

If you write it as a concurrent signal assignment
it acts as a process on its own, and therefore
executes just once at time 0.

why will it act once? wouldn't that a concurrent statement? so I guess
it should keep happening as long as other processes are running so
this statement (out of process) will be executed more than once.

Am I wrong?

Regards,
Amit

 

[Amit]

You said:

If you write [...] a concurrent signal assignment
it acts as a process on its own, and therefore
executes just once at time 0.

why will it act once? wouldn't that a concurrent statement? so I guess
it should keep happening as long as other processes are running so
this statement (out of process) will be executed more than once.

Am I wrong?

No, you're not completely wrong; but I was right too.
I forgot to mention one important detail....

Any VHDL concurrent assignment is simply shorthand for a
process, sensitive to every signal that appears on the
process's right-hand-side expression.  For example:

architecture blah of foo is
  ...
begin
  A <= B or C;
  ...

is shorthand for...

  process (B, C)
  begin
    A <= B or C;
  end process;

As I'm sure you know, this process...
- executes at time 0 from top to bottom
- then waits for a change (event) on any signal in
  its sensitivity list
- then loops around to the top and executes again
- and so on, for ever.

In fact, the process with its sensitivity list is
itself a shorthand for this version...

  process -- no sensitivity
  begin
    A <= B or C;
    wait on B, C;  -- wait for change on sensitivity list
  end process;

The "executes once at time zero" thing happens simply
because the sensitivity "wait on" is at the BOTTOM of
the process, not at the beginning.

This is fine, BUT what happens if there are NO signals
in the right-hand side expression?

 D <= '1', '0' after 10 ns;

This translates into

  process -- no sensitivity
  begin
    D <= '1', '0' after 10 ns;
    wait;   -- No sensitivity to wait on!!!!
  end process;

So, as I said, such a concurrent assignment will
execute just once at time zero.  It then freezes
forever at the implicit "wait" statement.

Hope that clarifies things.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Thanks! that was really helpful!

Last question (if you don't mind) is not related to this thread.

I have a software background and currently learning Digital design and
VHDL. Will that help me in future to get into embedded/digital field?
what would be a right step in order to get into this field?
I tried few times but what I really get back is that my background is
not embedded or hardware design so it seems it is really hard to get
into digital field.

Any advice will be appreciated.

Thanks.

 

[Tricky]

You said:
If you write [...] a concurrent signal assignment
it acts as a process on its own, and therefore
executes just once at time 0.
why will it act once? wouldn't that a concurrent statement? so I guess
it should keep happening as long as other processes are running so
this statement (out of process) will be executed more than once.
Am I wrong?

No, you're not completely wrong; but I was right too.
I forgot to mention one important detail....

Any VHDL concurrent assignment is simply shorthand for a
process, sensitive to every signal that appears on the
process's right-hand-side expression.  For example:

architecture blah of foo is
  ...
begin
  A <= B or C;
  ...

is shorthand for...

  process (B, C)
  begin
    A <= B or C;
  end process;

As I'm sure you know, this process...
- executes at time 0 from top to bottom
- then waits for a change (event) on any signal in
  its sensitivity list
- then loops around to the top and executes again
- and so on, for ever.

In fact, the process with its sensitivity list is
itself a shorthand for this version...

  process -- no sensitivity
  begin
    A <= B or C;
    wait on B, C;  -- wait for change on sensitivity list
  end process;

The "executes once at time zero" thing happens simply
because the sensitivity "wait on" is at the BOTTOM of
the process, not at the beginning.

This is fine, BUT what happens if there are NO signals
in the right-hand side expression?

 D <= '1', '0' after 10 ns;

This translates into

  process -- no sensitivity
  begin
    D <= '1', '0' after 10 ns;
    wait;   -- No sensitivity to wait on!!!!
  end process;

So, as I said, such a concurrent assignment will
execute just once at time zero.  It then freezes
forever at the implicit "wait" statement.

Hope that clarifies things.

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Thanks! that was really helpful!

Last question (if you don't mind) is not related to this thread.

I have a software background and currently learning Digital design and
VHDL. Will that help me in future to get into embedded/digital field?
what would be a right step in order to get into this field?
I tried few times but what I really get back is that my background is
not embedded or hardware design so it seems it is really hard to get
into digital field.

Any advice will be appreciated.

Thanks.

The problem you have is that a lot of people either learnt the basics
of digital electronics by programming for older systems, where
knowledge of how the system worked lead to far more efficient code
(though Im pretty sure this will still be the case) or learned them in
an engineering degree, which will be about 3 years of study. Im sure
you can learn it, but software experience can be a bit of a hinderance
(the concept of concurrency confuses and scares alot of software
engineers. Dont even start talking about processes being procedural,
that will just confuse them even more )

I dont have any advice on what books to go for, Im sure others can
point some out, but my advise would be to come at any project from the
top down. Imagine the circuit before you start writing the VHDL, even
down to the register level. Drawing it may make it easier. Most
digital designs are pipelines, which is almost the opposite of how
software is often written, and so a detail design diagram can help
massivly.

 

[Mike Treseler]

It is necessary but not sufficient.
Do some projects.

"embedded" connotes firmware design to me,
rather than fpga (which is usually considered hardware).
Firmware is bit level software that updates
volatile input and output registers
by polling or by interrupt service.

Im sure
you can learn it, but software experience can be a bit of a hinderance
(the concept of concurrency confuses and scares alot of software
engineers. Dont even start talking about processes being procedural,
that will just confuse them even more )

Actually, I have found that some firmware guys take
to procedural, single process vhdl code.
It is the port maps and wires that are
more of struggle.

-- Mike Treseler

 

[Amit]

It is necessary but not sufficient.
Do some projects.


"embedded" connotes firmware design to me,
rather than fpga (which is usually considered hardware).
Firmware is bit level software that updates
volatile input and output registers
by polling or by interrupt service.


Actually, I have found that some firmware guys take
to procedural, single process vhdl code.
It is the port maps and wires that are
more of struggle.

     -- Mike Treseler

Thanks to all.

Yes, I guess there is no short cut to it and I have to keep learning
and keep sending my resume and see what would happen!>

Merry Christmas everybody.