Test bench

Discussion in 'VHDL' started by john, Feb 23, 2009.

  1. john

    john Guest

    Hi,

    I am using ISE10.1 and simulating the code using its own behavioral
    simulator. It generated the VDHL test code for me which I modified and
    developed later. The Spartan is reading an 8 bit parallel data bus and
    write it to a RAM. I assigned the 8 bit parallel data bus with some
    numbers in the VHDL test bench and can see them in the simulator.

    Now, What I want to know is

    1. How can I make the VHDL test bench file to read my made text file
    and write the output results in the some text file too. Using ISE and
    Modelsim? How can I define the location where I want o store the file?
    Thanks
    John
     
    john, Feb 23, 2009
    #1
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  2. john wrote:

    > Now, What I want to know is
    >
    > 1. How can I make the VHDL test bench file to read my made text file
    > and write the output results in the some text file too.


    I would write a stimulus process and a checking process in vhdl,
    and an assert statement to check values.
    I would use the text as a comment.

    > Using ISE and Modelsim?


    Just modelsim and an editor.

    > How can I define the location where I want o store the file?


    Text from assert and report statements goes to the modelsim terminal.
    I can redirect it to a file if need be,
    but I only really need one bit of data: pass or fail.

    -- Mike Treseler

    testbench example here:
    http://mysite.verizon.net/miketreseler/
     
    Mike Treseler, Feb 23, 2009
    #2
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  3. john

    KJ Guest

    "john" <> wrote in message
    news:...
    > Hi,
    >
    > 1. How can I make the VHDL test bench file to read my made text file
    > and write the output results in the some text file too.


    For some basics on reading and writing files refer to
    http://www.eda.org/comp.lang.vhdl/FAQ1.html#files

    Likely you'll want to be able to read and write std_logic_vector types since
    that is likely the data type for your RAM I/O. Google for something like
    "convert std_logic_vector to string" and you will probably be able to find a
    package of functions that someone has put together that you can use. Things
    like std_logic, integer, time (i.e. basic types that aren't vectors) can be
    easily converted to strings like this
    std_logic'image(xyz)
    integer'image(xyz)
    time'image(xyz)

    But std_logic_vector'image(xyz) is not valid. It's not too difficult to
    write your own function that loops through the elements of a
    std_logic_vector assembling the string bit at a time...but then you'll be
    asking for how to do this in hex...so like I said, Google a bit to see how
    others have done it and you'll be moving up the learning curve as you do so.
    Once you have such a package of your own you can reuse it on anything in the
    future as well and will be part of your own personal toolkit of "things that
    I wish I didn't have to create from scratch, but I did".

    > Using ISE and
    > Modelsim?


    Modelsim

    > How can I define the location where I want o store the file?

    That is part of the file_open function that is part of the VHDL language.
    One of the parameters is the file/path name.

    Also consider Mike's suggestion. Many times the reason people have for
    wanting file I/O is for the purposes of verifying that their designs are
    working correctly. But this can be done without any file I/O by creating a
    testbench for your design that generates known stimulus and checks that the
    outputs are correct using VHDL asserts.
    Kevin Jennings
     
    KJ, Feb 25, 2009
    #3
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