# Test vector for only MSB being set.

Discussion in 'VHDL' started by Niv (KP), Feb 3, 2009.

1. ### Niv (KP)Guest

I have a function which accepts an unsigned vector of unconstrained
length, and assigns it to the variable "work".

One of the operations it performs depends on the value being
"1000......0000"
that is all '0's axcept the msb being set to a '1' , for any length
vector

I currently test for this as follows:

ELSIF ((work(work'HIGH) = '1')) AND
((work(work'HIGH - 1 DOWNTO work'LOW)) = (work(work'HIGH - 1
DOWNTO work'LOW)'RANGE => '0')) THEN
-- operation here

This compiles OK, but is there a neater way, it does seem a bit long
winded.

Regards, Kev P.

Niv (KP), Feb 3, 2009

2. ### TrickyGuest

On 3 Feb, 13:45, "Niv (KP)" <> wrote:
> I have a function which accepts an unsigned vector of unconstrained
> length, and assigns it to the variable "work".
>
> One of the operations it performs depends on the value being
> "1000......0000"
> that is all '0's axcept the msb being set to a '1' , for any length
> vector
>
> I currently test for this as follows:
>
> ELSIF ((work(work'HIGH) = '1')) AND
>         ((work(work'HIGH - 1 DOWNTO work'LOW)) = (work(work'HIGH - 1
> DOWNTO work'LOW)'RANGE => '0'))      THEN
>   -- operation here
>
> This compiles OK, but is there a neater way, it does seem a bit long
> winded.
>
> Regards, Kev P.

how about changing:
((work(work'HIGH - 1 DOWNTO work'LOW)) = (work(work'HIGH - 1 DOWNTO
work'LOW)'RANGE => '0'))

to

to_integer( ((work(work'HIGH - 1 DOWNTO work'LOW)) ) = 0;

Thats about as compact as it can get. I can only suggest setting up
aliases for the MSB and lower bits, so it reads:

alias MSB : std_logic is work(work'high);
alias LSBs : unsigned(work'HIGH - 1 DOWNTO work'LOW ) is work
(work'HIGH - 1 DOWNTO work'LOW);

elsif MSB = '1' and to_integer(LSBs) = 0 then

This is just reorganisation of the "wind".

Tricky, Feb 3, 2009

3. ### Niv (KP)Guest

On 3 Feb, 14:17, Jonathan Bromley <>
wrote:
> On Tue, 3 Feb 2009 05:45:54 -0800 (PST), "Niv (KP)"
>
> <> wrote:
> >I have a function which accepts an unsigned vector of unconstrained
> >length, and assigns it to the variable "work".

>
> >One of the operations it performs depends on the value being
> >"1000......0000"
> >that is all '0's axcept the msb being set to a '1' , for any length
> >vector

>
> Awkward.  Is this any help?
>
>   if vec = (1 => '1', 2 to vec'length => '0') then ...
>
> My instinct tells me it is better to write a function:
>
>   function msb_only(n: positive) return std_logic_vector is
>     variable it: std_logic_vector(1 to n);
>   begin
>     it := (1 => '1', 2 to n => '0');
>     return it;
>   end;
>   ...
>     if vec = msb_only(vec'length) then ...
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> ://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

The "TO_INTEGER" looks promising, but I've changed it as follows (for
my unique case);

....
ELSIF TO_INTEGER(work) = 2**(work'HIGH) THEN
.....

Kev P.

Niv (KP), Feb 3, 2009

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