Test vectors for emulator.

Discussion in 'VHDL' started by Slawek, May 11, 2007.

  1. Slawek

    Slawek Guest

    Hello!
    My question is:

    What is the most popular technique of producing and applying test vectors to
    emulated design?
    I assume that one of the following solutions can be used:

    1. Dumping test vectors from behavioral testbench during simulation.
    Applying from a file to emulated design.
    2. Designing RTL testbench and emulating along with the design. Obtaining
    PASSED/FAILED status from emulator.
    3. Connecting emulator to real system (dealing with reduced speed (1 MHz) of
    the emulated design).
    4. Others?

    I know that many engineers put the big emulator boxes in a corner and use
    them most often as a stool ~:).
    Hopefully, someone has other experience and would like to share it with me.

    Thanks in advance!
    Slawek
    Slawek, May 11, 2007
    #1
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  2. Slawek wrote:

    > What is the most popular technique of producing and applying test vectors to
    > emulated design?


    Don't know. I use procedures.
    See the testbench here:

    http://home.comcast.net/~mike_treseler/

    -- Mike Treseler
    Mike Treseler, May 11, 2007
    #2
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