Testbench doubt

Discussion in 'VHDL' started by VHDL User, Aug 18, 2004.

  1. VHDL User

    VHDL User Guest

    Hi all,
    Suppose I want to write a testbench for a design that simulates the
    design for a suffciently long time,so that wait for <t> statements are
    obv. inadequate .Will a statement
    wait;
    do the job?
    as in causing simulation to run forever?
    An y other ideas as to how a long simulation time may be met ?
     
    VHDL User, Aug 18, 2004
    #1
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  2. VHDL User wrote
    > An y other ideas as to how a long simulation time may be met ?


    The simulation will continue until
    all processes reach a wait statement.

    If one process, say the simulation clock,
    never reaches a wait, the simulation
    will run indefinitely.

    -- Mike Treseler
     
    Mike Treseler, Aug 18, 2004
    #2
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  3. VHDL User

    Niels Bakker Guest

    Mike Treseler wrote:
    > VHDL User wrote
    >
    >>An y other ideas as to how a long simulation time may be met ?

    >
    >
    > The simulation will continue until
    > all processes reach a wait statement.
    >
    > If one process, say the simulation clock,
    > never reaches a wait, the simulation
    > will run indefinitely.
    >
    > -- Mike Treseler


    If all your processes are synchronous, and suppose your clock signal is
    called 'clk' and of type std_logic.

    Use a boolean signal 'simulate' as follows:

    ....
    simulate <= true, false after 2 ms;
    clk <= NOT clk after 5 ns WHEN simulate ELSE '0';
    ....

    Your simulation will end after 2 ms, since the clock stops running and
    there are no other stimuli left.

    Niels Bakker
     
    Niels Bakker, Aug 19, 2004
    #3
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