Testbench help

Discussion in 'VHDL' started by Matt Boland, Jan 23, 2005.

  1. Matt Boland

    Matt Boland Guest

    Hi All,


    I'm new to VHDL, and I'm having a little trouble understanding how the
    testbench is meant to work.

    I'm using Xilinx ISE as my IDE.

    I created my synthesizable design and it synthesises ok and I can fit
    it, etc. It is a bridge between two busses.

    I can generate a skeleton testbench for my design and add statements,
    etc. to it that drives my design. This works ok. In the testbench there
    is some logic that emulates one of the busses, and other logic that
    emulates the other bus.

    However, now I want to break my testbench into units. I want to put both
    bus emulators into their own seperate vhdl files and then just
    instantiate them in the main testbench. This is where I'm having
    trouble. I can do the behavioral simulation, but not the post-fit
    simulation. Modelsim wants to find the bus1_timesim.vhd and
    bus2_timesim.vhd files, etc.

    All the timing information is included in my bus emaulator vhdl files. I
    need to be able to tell ISE/Modelsim that these files are part of the
    testbench and not part of the UUT. They are in my project as testbench
    files and not design files.

    Am I missing something?

    Matt Boland
    Matt Boland, Jan 23, 2005
    #1
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  2. Matt Boland wrote:

    > I'm new to VHDL, and I'm having a little trouble understanding how
    > the testbench is meant to work.


    It wiggles the UUT inputs and watches the outputs.

    > I created my synthesizable design and it synthesises ok and I can fit
    > it, etc. It is a bridge between two busses.
    > I can generate a skeleton testbench for my design and add statements,
    > etc. to it that drives my design. This works ok. In the testbench there
    > is some logic that emulates one of the busses, and other logic that
    > emulates the other bus.


    Good work.

    > However, now I want to break my testbench into units.


    That might be an unnecessary complication.
    Consider adding procedures to the main
    testbench process or perhaps an extra
    process or two to the testbench architecture.

    > I want to put both
    > bus emulators into their own seperate vhdl files and then just
    > instantiate them in the main testbench.


    For the UUT and purchased models
    some hierarchy and signal spaghetti
    is required. For a one-off testbench
    it is certain pain and doubtful gain.

    -- Mike Treseler
    Mike Treseler, Jan 23, 2005
    #2
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