testbench procedure trouble

Discussion in 'VHDL' started by Toby, Feb 11, 2005.

  1. Toby

    Toby Guest

    Hi, I'm kinda new to this whole testbench thing. I have a procedure in
    my testbench that looks something like this:

    procedure SMP_READ
    (
    signal A_P_SMP_DATA_READ: out std_logic_vector(7 downto 0);
    ) is
    begin

    A_P_SMP_DATA_READ(7) <= A_SMP_DATA7;
    A_P_SMP_DATA_READ(6) <= A_SMP_DATA6;
    A_P_SMP_DATA_READ(5) <= A_SMP_DATA5;
    A_P_SMP_DATA_READ(4) <= A_SMP_DATA4;
    A_P_SMP_DATA_READ(3) <= A_SMP_DATA3;
    A_P_SMP_DATA_READ(2) <= A_SMP_DATA2;
    A_P_SMP_DATA_READ(1) <= A_SMP_DATA1;
    A_P_SMP_DATA_READ(0) <= A_SMP_DATA0;

    end SMP_READ;

    Where A_SMP_DATA7, A_SMP_DATA6......A_SMP_DATA0 are signals assigned
    for the entire testbench (between the component declarations and the
    procedure declarations) as follows:

    signal A_SMP_DATA0 : STD_LOGIC := 'L';
    signal A_SMP_DATA1 : STD_LOGIC := 'L';
    signal A_SMP_DATA2 : STD_LOGIC := 'L';
    signal A_SMP_DATA3 : STD_LOGIC := 'L';
    signal A_SMP_DATA4 : STD_LOGIC := 'L';
    signal A_SMP_DATA5 : STD_LOGIC := 'L';
    signal A_SMP_DATA6 : STD_LOGIC := 'L';
    signal A_SMP_DATA7 : STD_LOGIC := 'L';

    The problem is, A_P_SMP_DATA_READ(7..0) is not getting the values
    assigned to it in the procedure. I can set a breakpoint (Aldec
    Active-HDL) near the end of the procedure, and I run the cursor over
    the A_P_SMP_DATA_READ(#) and the A_SMP_DATA#, and they just arent
    equal. How can that even be? If I say A_P_SMP_DATA_READ(7) <=
    A_SMP_DATA7; then shouldn't those two things be equal? Any ideas
    would be greatly appreciated.
    Toby, Feb 11, 2005
    #1
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