Testbench waveform problem, please help..

Discussion in 'VHDL' started by shashankrsharma, Mar 21, 2009.

  1. shashankrsharma

    shashankrsharma

    Joined:
    Mar 1, 2009
    Messages:
    6
    The below code reads data from file,and displays in TestBench Waveform, as std_logic_vector.. the program is synthesized and worked properly but "TestBench did not execute", the error is:

    --ERROR -------------------------------------------
    Running Fuse ...
    Compiling vhdl file "C:/Xilinx/strTostdlogicvector/strTostdlogicvectortb.ant" in Library work.
    Entity <strtostdlogicvectortb> compiled.
    Entity <strtostdlogicvectortb> (Architecture <testbench_arch>) compiled.
    Parsing "strTostdlogicvectortb_gen.prj": 0.05
    Codegen work/strTostdlogicvectortb: 0.00
    Codegen work/strTostdlogicvectortb/testbench_arch: 0.36
    Building strTostdlogicvectortb_tbxr.exe
    Running ISim simulation engine ...
    This is a Lite version of ISE Simulator:
    Simulator is doing circuit initialization process.
    Finished circuit initialization process.

    ** Failure:Success! Simulation for annotation completed
    User(VHDL) Code Called Simulation Stop


    Simulation stopped when executing process: strTostdlogicvectortb.ant:105
    on line 131 in file "C:/Xilinx/strTostdlogicvector/strTostdlogicvectortb.ant"

    -------------------------------------------------------------------------------------------------------

    For reference the code is give below->


    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    USE IEEE.STD_LOGIC_TEXTIO.ALL;
    use std.textio.all;
    entity strTostdlogicvector is
    Port ( clock : in STD_LOGIC;
    inp: in std_logic:='1';
    outp : out STD_LOGIC_VECTOR (35 downto 1));
    end strTostdlogicvector;

    architecture Behavioral of strTostdlogicvector is
    FILE RESULTS: TEXT OPEN WRITE_MODE IS "C:\Xilinx\strTostdlogicvector\outfile.txt";
    FILE RESULTS1: TEXT OPEN READ_MODE IS "C:\Xilinx\strTostdlogicvector\infile.txt";
    begin
    process(clock)
    type chararray is Array(35 downto 1) of character;
    variable TX_OUT1,TX_OUT2: LINE ;
    variable ii:chararray;
    variable sl: std_logic;
    begin

    if(clock='1' and clock'event and inp='1') then

    STD.TEXTIO.readline(RESULTS1, TX_OUT1);
    for j in 1 to 35 loop
    STD.TEXTIO.read(TX_OUT1,ii(j));
    end loop;

    for i in 1 to 35 loop

    if(ii(i) = '0') then
    STD.TEXTIO.write(TX_OUT2,string'("0"));
    STD.TEXTIO.writeline(RESULTS, TX_OUT2);
    sl:='0';
    else
    STD.TEXTIO.write(TX_OUT2, string'("1"));
    STD.TEXTIO.writeline(RESULTS, TX_OUT2);
    sl:='1';
    end if;
    outp(i)<=sl;
    end loop;

    end if;
    end process;
    end Behavioral;

    --------------------------------------------------------------------------------------------
    The input file contains:

    1 0 1 1 0 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
    1 0 1 1 0 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
     
    shashankrsharma, Mar 21, 2009
    #1
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