Testing an AHB slave after synthesis

Discussion in 'VHDL' started by Ludek, Apr 7, 2010.

  1. Ludek

    Ludek

    Joined:
    Apr 7, 2010
    Messages:
    1
    Hi people,

    I develop an AHB slave with a framework. So the slave has generally one input (ahb_slv_in_type) and one output (ahb_slv_out_type). But (as most of you know) this is a wide bus, therefore after synthesis I get lots of single signals and I cannot simulate it with the framework again. Is there any way to keep these signals in one bus as it was before synthesis? I use Synplify PRO and ModelSim but I have not found in manuals anything helpful.

    Any help is very appreciated.
    Thanks
    Ludek, Apr 7, 2010
    #1
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