Testing and finding the error in my design (THINK it's in the presampler/ringbuffer)

Discussion in 'VHDL' started by Preben Holm, Apr 25, 2005.

  1. Preben Holm

    Preben Holm Guest

    Hi

    I'm building the digital part of an oscilloscope (as already written in
    earlier posts).
    For this I have a trigger, a memory management unit and a presample unit
    (basically a ringbuffer).

    I've tested the ringbuffer by setting a slow varying signal
    (square-pulse) on the A/D converter and then writing out the output to 8
    diodes. Changing the pulse to fx. triangular I see the signal change on
    the diodes a lot later (can't simulate the block memory in modelsim).
    This thing really works (doing a lot of stuff)

    But when putting this part together with the mmu-unit as this:
    -----
    memoryunit : mmut
    port map ( clk => clk,
    reset => reset,
    prescale => prescale,
    trig => trig,
    read => read,
    trigged => trigged,
    holdoff_select => holdoff_select,
    saved => saved,
    rclk => rclk,
    radr => radr,
    din => sample_delayed,
    dout => dout );


    presampleunit : presampler
    port map ( clk => clk,
    reset => reset,
    prescale => prescale,
    pretrigger => pretrigger_select,
    din => din,
    dout => sample_delayed);
    -----

    I get some real strange trigger-positions that aren't the same for each
    trigger, and a little mis-placed signal somewhere in the signal (but
    else the sampled signal is just fine actually) - like


    /\ /\ /\
    / \ / \ / \
    / \ / / \
    / \ / / / \
    / \ / / \ / \
    / \ / \ / \
    / \/ \/ \



    It's strange... My first idea was that the signal wasn't saved correctly
    and just kept saving the signal over and over the same memory while
    reading a lot faster the little part of the signal was a new part that
    was being written, but I guess that this would look more like this:

    /\ /\
    / \ / \
    / \ / \
    / \ / / \
    / \ / \ / \
    / \ / \ / \ /
    / \/ \/ \/


    So this error is probably not the correct one.

    So I decided to try deactivating the ringbuffer (presampler module)
    so my code looked like this:
    -----
    memoryunit : mmut
    port map ( clk => clk,
    reset => reset,
    prescale => prescale,
    trig => trig,
    read => read,
    trigged => trigged,
    holdoff_select => holdoff_select,
    saved => saved,
    rclk => rclk,
    radr => radr,
    din => din, ------ THIS IS THE EDITING LINE
    dout => dout );


    presampleunit : presampler
    port map ( clk => clk,
    reset => reset,
    prescale => prescale,
    pretrigger => pretrigger_select,
    din => din,
    dout => sample_delayed);
    -----

    So now it works fine - but no prescaler (the trigger is very fine cut on
    the right level, so this is very nice)

    I get the trigger the correct place and no strange signals in the
    transferred signal:

    /\ /\ /\
    / \ / \ / \
    / \ / \ / \
    / \ / \ / \
    / \ / \ / \
    / \ / \ / \
    / \/ \/ \

    So now I ask, where is the error, and where should I be looking.
    I will publish all of my project code to you wise guys if this is
    necessary, but here is the code of the presampler/ringbuffer:

    -----
    entity presampler is
    Port ( clk : in std_logic;
    reset : in std_logic;
    prescale : in std_logic;
    pretrigger : in std_logic_vector(3 downto 0);
    din : in std_logic_vector(7 downto 0);
    dout : out std_logic_vector(7 downto 0));
    end presampler;


    architecture Behavioral of presampler is
    signal addra : std_logic_vector(10 downto 0);
    signal addrb : std_logic_vector(10 downto 0);
    signal pretrigger_i : std_logic_vector(11 downto 0);

    component counter11bit
    Port ( clk, ce, reset : in std_logic;
    preset : in std_logic_vector(11 downto 0);
    c : out std_logic;
    q : out std_logic_vector(10 downto 0));
    end component;

    component fifo_mem
    port ( ADDRA : in std_logic_vector (10 downto 0);
    ADDRB : in std_logic_vector (10 downto 0);
    CLKA : in std_logic;
    CLKB : in std_logic;
    DIA : in std_logic_vector (7 downto 0);
    ENA : in std_logic;
    ENB : in std_logic;
    SSRA : in std_logic;
    SSRB : in std_logic;
    WEA : in std_logic;
    DOB : out std_logic_vector (7 downto 0));
    end component;

    begin

    -- every time there is a 'sample' signal, the counters should count
    -- and save it into the "fifo".

    presamplevalue : process(clk)
    begin
    if rising_edge(clk) then
    case pretrigger is
    when "0000" => pretrigger_i <= "000000001010"; -- 10
    when "0001" => pretrigger_i <= "000000010100"; -- 20
    when "0010" => pretrigger_i <= "000000011110"; -- 30
    when "0011" => pretrigger_i <= "000000101000"; -- 40
    when "0100" => pretrigger_i <= "000000110010"; -- 50
    when "0101" => pretrigger_i <= "000000111100"; -- 60
    when "0110" => pretrigger_i <= "000001000110"; -- 70
    when "0111" => pretrigger_i <= "000001010000"; -- 80
    when "1000" => pretrigger_i <= "000001011010"; -- 90
    when "1001" => pretrigger_i <= "000001100100"; -- 100
    when "1010" => pretrigger_i <= "000011001000"; -- 200
    when "1011" => pretrigger_i <= "000100101100"; -- 300
    when "1100" => pretrigger_i <= "000110010000"; -- 400
    when "1101" => pretrigger_i <= "000111110100"; -- 500
    when "1110" => pretrigger_i <= "001001011000"; -- 600
    when "1111" => pretrigger_i <= "001010111100"; -- 700
    when others => pretrigger_i <= "000000001010"; -- 10
    end case;
    end if;
    end process;


    -- Counters for addressing memory
    addressB : counter11bit
    port map ( clk => clk,
    ce => prescale,
    reset => reset,
    preset => "000000000000",
    c => open,
    q => addrb);

    addra <= addrb + pretrigger_i;


    fifomemory : fifo_mem
    port map ( ADDRA => addra,
    ADDRB => addrb,
    CLKA => clk,
    CLKB => clk,
    DIA => din,
    ENA => '1',
    ENB => '1',
    SSRA => reset,
    SSRB => reset,
    WEA => prescale,
    DOB => dout);

    end Behavioral;
    -----

    The counter module is just a simple counter for addressing the memory:

    -----
    process(clk, reset)
    begin
    if rising_edge(clk) then
    if (reset = '1') then
    count <= preset;
    else
    if (ce = '1') then
    count <= count + 1;
    if (count(11) = '1') then -- this is the old count-value
    count <= preset;
    end if;
    end if;
    end if;
    end if;
    end process;

    q <= count(10 downto 0);
    c <= count(11);
    -----


    The code of the fifo_mem is quite long (but actually it's just a
    ramb_s9_s9) with some ports left open!



    Hope you guys/girls out there can help me!
    It's really beginning to anoy me now


    And like always: Thanks for helping me.

    Preben Holm
     
    Preben Holm, Apr 25, 2005
    #1
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  2. Preben Holm

    Jim George Guest

    Re: Testing and finding the error in my design (THINK it's in thepresampler/ringbuffer)

    > the diodes a lot later (can't simulate the block memory in modelsim).

    Why not? If you are getting library errors, one common mistake is to do
    an IP update of ISE without updating the Modelsim precompiled libraries
    (if you're using MXE) or recompiling the libraries from source (if
    you're using PE or SE). This does not cause problems when simulating
    synthesized code, only when your code has instantiated components from
    Unisim or Simprim.

    I couldn't find anything wrong with your code, but I didn't do an
    in-depth search.
     
    Jim George, Apr 26, 2005
    #2
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  3. Preben Holm

    Preben Holm Guest

    Re: Testing and finding the error in my design (THINK it's in thepresampler/ringbuffer)

    Jim George wrote:
    >> the diodes a lot later (can't simulate the block memory in modelsim).

    >
    >
    > Why not? If you are getting library errors, one common mistake is to do
    > an IP update of ISE without updating the Modelsim precompiled libraries
    > (if you're using MXE) or recompiling the libraries from source (if
    > you're using PE or SE). This does not cause problems when simulating
    > synthesized code, only when your code has instantiated components from
    > Unisim or Simprim.
    >
    > I couldn't find anything wrong with your code, but I didn't do an
    > in-depth search.


    I may have found out, when making the PROM-file the tool doesn't
    actually overwrite the file!!!
    I have it working now, after removing the old PROM-file!
    I wrote the prom all times in the last couple of times since I found it
    annoying not being able to reset the circuit.


    Thanks for looking through my code anyway!
     
    Preben Holm, Apr 28, 2005
    #3
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