Testing VHDL Module

[Paul Hogan]

Hi,

I'm pretty new to VHDL and I need to implement a slave OPB core for a
Microblaze system. I've got a couple of good books on VHDL which
should see me ok on the language side but can anyone offer any advice
on how to go about testing the design to make sure it does what it
should - this is a bit of a grey area for me coming from a software
background.

I guess what I need to be able to do is vary the inputs to my device
and look at the outputs. I'll be using the ISE tools from Xilinx but
I'm not sure what tools are available to test and give me some
confidence in my code.

Any advice and opinions will be most gratefully received.

TIA,

PH.

 

[rickman]

Hi,

I'm pretty new to VHDL and I need to implement a slave OPB core for a
Microblaze system. I've got a couple of good books on VHDL which
should see me ok on the language side but can anyone offer any advice
on how to go about testing the design to make sure it does what it
should - this is a bit of a grey area for me coming from a software
background.

I guess what I need to be able to do is vary the inputs to my device
and look at the outputs. I'll be using the ISE tools from Xilinx but
I'm not sure what tools are available to test and give me some
confidence in my code.

Any advice and opinions will be most gratefully received.

I don't know that I can answer your question in any simple way. But I
will give you these pointers.

1) I am beginning to think that the cardinal rule of coding for
synthesis is to first determine the register level hardware design, and
then code in your HDL. Remember what HDL stands for Hardware
Description Language. It is not a programming language : when
synthesizing your code it is for *describing* the hardware. This is
very important and your software background may put you at a
disadvantage. I know that even though I am a hardware guy my software
experience made it hard for me to learn VHDL at first since it is little
like a "normal" language.

2) Now that said, you can also treat the language as a programming
language for test bench and other non-synthesis purposes. You can
describe the function of the external interfaces without coding
registers and such. This will simulate just fine. Another way to do it
is to think of the system under test as one functional block with inputs
and outputs. You can apply a vector of inputs, clock it and read a
vector of outputs to verify. I don't think this will be easy if your
external interfaces don't all use the same clock.

--

Rick "rickman" Collins

(e-mail address removed)
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Eric]

Paul,

I guess what I need to be able to do is vary the inputs to my device
and look at the outputs.

The Xilinx ISE provides a simulator called Modelsim. It is used to
toggle the inputs of an entity and view the resulting outputs.

Eric.

 

[tesla]

I don't know that I can answer your question in any simple way. But I
will give you these pointers.

1) I am beginning to think that the cardinal rule of coding for
synthesis is to first determine the register level hardware design, and
then code in your HDL. Remember what HDL stands for Hardware
Description Language. It is not a programming language : when
synthesizing your code it is for *describing* the hardware. This is
very important and your software background may put you at a
disadvantage. I know that even though I am a hardware guy my software
experience made it hard for me to learn VHDL at first since it is little
like a "normal" language.

2) Now that said, you can also treat the language as a programming
language for test bench and other non-synthesis purposes. You can
describe the function of the external interfaces without coding
registers and such. This will simulate just fine. Another way to do it
is to think of the system under test as one functional block with inputs
and outputs. You can apply a vector of inputs, clock it and read a
vector of outputs to verify. I don't think this will be easy if your
external interfaces don't all use the same clock.

--

I read you many times saying same thing and I am sure it is really
important and it is most common-classical newbie problem.

I am trying to learn VHDL but I have to learn first what code infers
what hardware.I mean I do not know which statements causes a FF, latch
or register or whatever exists in electronics.

By the way when we say register, Does it mean several FFs in parallel?
What does it mean exacly register level hardware design?

Ok. I can think the design in hardware but how can I know the code ?

I am reading tutorials but I could not find any specific and complete
description of

VHDL <= Hardware
Hardware <= VHDL reference.

If you have, please give link(s).In fact I am drown in tutorials and
books.

Thanks A lot for your patient and helpful messages.

yusuf

 

[Mike Treseler]

I am trying to learn VHDL but I have to learn first what code infers
what hardware.I mean I do not know which statements causes a FF, latch
or register or whatever exists in electronics.

I am reading tutorials but I could not find any specific and complete
description of

VHDL <= Hardware
Hardware <= VHDL reference.

Synthesis manuals have this sort of information.
Also look at some code examples:
http://groups.google.com/groups?q=vhdl+treseler+rising_edge+clock+OR+clk
Good luck.

-- Mike Treseler

 

[rickman]

I read you many times saying same thing and I am sure it is really
important and it is most common-classical newbie problem.

Yeah, I am surprised to find myself repeating this so often. But it
seems to be a point of advice that is very often needed by newbies. I
think this is because (at least in my case) prior experience with
software points you in the wrong direction compared to an HDL which is
not really like software at all. Sorry if I have been redundant.

I am trying to learn VHDL but I have to learn first what code infers
what hardware.I mean I do not know which statements causes a FF, latch
or register or whatever exists in electronics.

That is available in all text books and synthesis tool user guides.
There are several variations on registers with async or sync reset/set,
enable or load control. So I can't give you examples for all of them.
But it shouldn't be too hard to find. I know Xilinx has some good notes
available at a link that was posted in another thread, although I found
some errors in some of the Xilinx material. The thread was asking about
inferring latchs without a warning message. One of the Xilinx style
guides I found actually gave the same code that the OP was getting the
warning on where he left out the ELSE condition.

By the way when we say register, Does it mean several FFs in parallel?
What does it mean exacly register level hardware design?

Register does not need to be multiple FFs. Register means an edge
triggered FF contrasted with a level sensitive latch. Register level
design or actually "Register Transfer Level" design (RTL) means you
specifically code the registers and the describe the logic between the
registers. This is in contrast to just trying to describe the behavior
of the circuit using any HDL features and structure that works.

Ok. I can think the design in hardware but how can I know the code ?

I am reading tutorials but I could not find any specific and complete
description of

VHDL <= Hardware
Hardware <= VHDL reference.

This is a link to the most recent Xilinx XST compiler guide on the web.
It is html and not pdf so it will be hard to save for viewing offline
(!$*%#**).

http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/xst/xst0001_1.html

Ok, I found a link to PDF files and the XST manual seems to be there.
There is a whole chapter on "HDL Coding Techniques" with examples on
every part.

http://support.xilinx.com/support/sw_manuals/xilinx6/download/

The last modified date on the XST manual is 8/04, so it should be up to
date, but it still has the error on latch synthesis which will generate
warnings in XST. My experience is that XST is very good about pointing
out your shortcomings as a VHDL programmer. I had some code that worked
in modelsim and Quartus without warning and I got lots of valid errors
in XST. So this should be a good tool to test your skills.


--

Rick "rickman" Collins

(e-mail address removed)
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

I forgot to give you another very useful link to the comp.lang.vhdl
FAQ.

http://www.eda.org/comp.lang.vhdl/

--

Rick "rickman" Collins

(e-mail address removed)
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX