tetst bench

Discussion in 'VHDL' started by craigs2, Mar 29, 2006.

  1. craigs2

    craigs2

    Joined:
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    Afternoon chaps, i am struggling a little to come up with a suitable test bench, i have written the code for a 12x16 RAM but not sure how to come up with the correct test bench, any ideas?

    entity RAM16x12 is
    port (address: in integer range 0 to 15;
    Data: inout std_ulogic_vector(11 downto 0);
    CS, WE, OE: in std_ulogic);
    end entity RAM16x12;

    architecture RTL of RAM16x12 is
    begin
    p0: process (address, CS, WE, OE) is
    type ram_array is array (0 to 15) of
    std_ulogic_vector(11 downto 0);
    variable mem: ram_array;
    begin
    Data <= (others => 'Z');
    if CS = '0' then
    if OE = '0' then
    Data <= mem(address);
    elsif WE = '0' then
    mem(address) := Data;
    end if;
    end if;
    end process p0;
    end architecture RTL;
     
    craigs2, Mar 29, 2006
    #1
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