TEXTIO drives me crazy!

Discussion in 'VHDL' started by brawnyboy, Oct 18, 2009.

  1. brawnyboy

    brawnyboy

    Joined:
    Oct 18, 2009
    Messages:
    1
    Hi all,

    I wrote a small vhdl code yesterday, and it didn't behave as expected. So I decided to write some debug comment in a file, to see what was going on.. Unfortunatelly I can not manage to make it work.. ModelSim doesn't stop to tell me :

    ** Error: C:/altera/Design_for_integrated_systems/hexprinter.vhd(48): Prefix of indexed name must be an array.

    Looks like it is not able to find the procedure write.. But this procedure exists, I checked in the TEXTIO library.. Somebody could give me a hint? I am really lost...

    Here is my code:

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.numeric_std.all;

    USE std.textio.all;

    ENTITY hexprinter IS
    PORT(
    -- Avalon interfaces signals
    clk : IN std_logic;
    nReset : IN std_logic;
    chipSelect : IN std_logic;
    write : IN std_logic;
    writeData : IN std_logic_vector (7 DOWNTO 0);
    -- OutPut
    dataOut: OUT std_logic_vector(6 DOWNTO 0)
    );
    End hexprinter;

    ARCHITECTURE comp OF hexprinter IS
    SIGNAL internValue: std_logic_vector(6 DOWNTO 0);
    -- LookUpTable
    TYPE LookUpTable IS ARRAY(0 TO 9) OF std_logic_vector(6 DOWNTO 0);
    CONSTANT table: LookUpTable := ("1000000", "1111001", "0100100", "0110000", "0011001", "0010010", "0000010", "1111000", "0000000", "0010000");
    BEGIN
    -- Update internValue
    PROCESS(clk, nreset)
    BEGIN
    IF (nReset = '0') THEN
    internValue <= (OTHERS => '0');
    ELSIF ( rising_edge(clk) ) THEN
    IF chipSelect = '1' AND write = '1' THEN
    internValue <= table( to_integer( unsigned( writeData(6 DOWNTO 0) ) ) );
    END IF;
    END IF;
    END PROCESS;

    -- Display internValue on the output
    dataout <= internValue;

    -- DEBUGGING
    PROCESS(writeData)
    use std.textio.all;
    variable li : line;
    FILE output : text OPEN WRITE_MODE IS "Output.txt";
    BEGIN
    WRITE(li, string'(" -> "));
    WRITE(li, integer'image( to_integer( unsigned( writeData(6 DOWNTO 0) ) ) ) );
    WRITE(li, " ==> ");
    FOR i in internValue'range LOOP
    WRITE(li, std_logic'image( internValue(i) ) );
    END LOOP;

    writeline(output, li);
    END PROCESS;
    END comp;
    brawnyboy, Oct 18, 2009
    #1
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