TextIO Tutorial

Discussion in 'VHDL' started by Dek, Apr 22, 2009.

  1. Dek

    Dek Guest

    Hi everybody,

    I'm new to VHDL an to this group too; as an exercise I'm trying to
    import data from several files using package TextIO, but I haven't
    found yet a good manual or tutorial about it; may you suggest me some?

    Thanks

    Bye

    Dek
    Dek, Apr 22, 2009
    #1
    1. Advertising

  2. Dek wrote:

    > I'm new to VHDL an to this group too; as an exercise I'm trying to
    > import data from several files using package TextIO, but I haven't
    > found yet a good manual or tutorial about it; may you suggest me some?


    When I want to work with files and data, i use python or perl.
    If I want to make a hardware model, I use vhdl.

    -- Mike Treseler
    Mike Treseler, Apr 22, 2009
    #2
    1. Advertising

  3. Dek

    Tricky Guest

    On 22 Apr, 08:57, Dek <> wrote:
    > Hi everybody,
    >
    > I'm new to VHDL an to this group too; as an exercise I'm trying to
    > import data from several files using package TextIO, but I haven't
    > found yet a good manual or tutorial about it; may you suggest me some?
    >
    > Thanks
    >
    > Bye
    >
    > Dek


    If you're only trying to read in text, then TextIO is what you need.
    For binary files, you dont use the TextIO package, and reading data in
    is a bit more contrived and apparently doesnt work the same accross
    different apps. (as a note, I have functions to read/write bitmap
    files directly from VHDL in Modelsim but thats only because I work
    with video and looking at an actual picture is alot quicker than
    trying to interpret text).

    But like Mike says, if its for anything other than input to a hardware
    model, use something else to do the work. It might be best to just ask
    the questions here, or go on the Doulos VHDL courses.
    Tricky, Apr 22, 2009
    #3
  4. Dek

    Dek Guest

    On 22 Apr, 18:24, Tricky <> wrote:
    > On 22 Apr, 08:57, Dek <> wrote:
    >
    > > Hi everybody,

    >
    > > I'm new to VHDL an to this group too; as an exercise I'm trying to
    > > import data from several files using package TextIO, but I haven't
    > > found yet a good manual or tutorial about it; may you suggest me some?

    >
    > > Thanks

    >
    > > Bye

    >
    > > Dek

    >
    > If you're only trying to read in text, then TextIO is what you need.
    > For binary files, you dont use the TextIO package, and reading data in
    > is a bit more contrived and apparently doesnt work the same accross
    > different apps. (as a note, I have functions to read/write bitmap
    > files directly from VHDL in Modelsim but thats only because I work
    > with video and looking at an actual picture is alot quicker than
    > trying to interpret text).
    >
    > But like Mike says, if its for anything other than input to a hardware
    > model, use something else to do the work. It might be best to just ask
    > the questions here, or go on the Doulos VHDL courses.



    Thanks for the answer,

    what I want to do actually is an hardware model using a .txt file for
    the testbench. I' m trying to read different lines from a single file,
    and different data from a single line, and writing the same. Where can
    I find Doulos VHDL courses?

    Thanks

    Bye
    Dek, Apr 23, 2009
    #4
  5. Dek

    Dek Guest

    On 23 Apr, 10:06, Dek <> wrote:
    > On 22 Apr, 18:24, Tricky <> wrote:
    >
    >
    >
    >
    >
    > > On 22 Apr, 08:57, Dek <> wrote:

    >
    > > > Hi everybody,

    >
    > > > I'm new to VHDL an to this group too; as an exercise I'm trying to
    > > > import data from several files using package TextIO, but I haven't
    > > > found yet a good manual or tutorial about it; may you suggest me some?

    >
    > > > Thanks

    >
    > > > Bye

    >
    > > > Dek

    >
    > > If you're only trying to read in text, then TextIO is what you need.
    > > For binary files, you dont use the TextIO package, and reading data in
    > > is a bit more contrived and apparently doesnt work the same accross
    > > different apps. (as a note, I have functions to read/write bitmap
    > > files directly from VHDL in Modelsim but thats only because I work
    > > with video and looking at an actual picture is alot quicker than
    > > trying to interpret text).

    >
    > > But like Mike says, if its for anything other than input to a hardware
    > > model, use something else to do the work. It might be best to just ask
    > > the questions here, or go on the Doulos VHDL courses.

    >
    > Thanks for the answer,
    >
    > what I want to do actually is an hardware model using a .txt file for
    > the testbench. I' m trying to read different lines from a single file,
    > and different data from a single line, and writing the same. Where can
    > I find Doulos VHDL courses?
    >
    > Thanks
    >
    > Bye- Nascondi testo citato
    >
    > - Mostra testo citato -



    For example I wrote this code:

    --------------------------------------------------------------------
    USE std.textio.all;

    ENTITY form_IO IS
    --empty
    END form_IO;


    ARCHITECTURE formatted OF form_IO IS
    BEGIN
    PROCESS IS


    FILE formout : Text ;
    VARIABLE int : Integer := 5 ;
    VARIABLE buf : Line ;
    VARIABLE fstatus : File_open_status ;

    BEGIN

    File_open(fstatus, formout, "C:/Users/Daniele/Desktop/Esercizi/
    form_io.txt", write_mode);

    L1:write (buf, "This is an example of formatted I/O");
    L2:writeline (formout, buf);
    L3:write (buf, "Integer int=");
    L4:write (buf, int);
    L5:writeline (formout, buf);
    L6:file_close(formout);
    wait;

    END PROCESS;

    END formatted;
    -----------------------------------------------------------------

    but I got the following error message:

    # ** Error: C:/Users/Daniele/Desktop/Esercizi/Format_IO.vhd(24):
    Subprogram 'write' is ambiguous.
    # ** Error: C:/Users/Daniele/Desktop/Esercizi/Format_IO.vhd(24): No
    feasible entries for subprogram "write".
    # ** Error: C:/Users/Daniele/Desktop/Esercizi/Format_IO.vhd(26):
    Subprogram 'write' is ambiguous.
    # ** Error: C:/Users/Daniele/Desktop/Esercizi/Format_IO.vhd(26): No
    feasible entries for subprogram "write".
    # ** Error: C:/Users/Daniele/Desktop/Esercizi/Format_IO.vhd(33): VHDL
    Compiler exiting

    where am I wrong?

    Thanks

    Bye
    Dek, Apr 23, 2009
    #5
  6. Dek

    Bert_Paris Guest

    Dek avait prétendu :
    > L1:write (buf, "This is an example of formatted I/O");


    You need to use qualified expressions :
    L1:write (buf, string'("This is an example of formatted I/O"));

    I personnaly use often the trick to concatenate a character.
    "Hello" & HT becomes automatically a string (it's not ambiguous any
    more)

    We teach this in the Doulos course ;-)

    Bert
    Bert_Paris, Apr 23, 2009
    #6
  7. Dek

    Dek Guest

    On 23 Apr, 11:22, Jonathan Bromley <>
    wrote:
    > On Thu, 23 Apr 2009 01:56:20 -0700 (PDT), Dek wrote:
    > >       File_open(fstatus, formout, ".../form_io.txt", write_mode);
    > >       L1:write (buf, "This is an example of formatted I/O");
    > >       L2:writeline (formout, buf);
    > >       L3:write (buf, "Integer int=");
    > >       L4:write (buf, int);
    > >       L5:writeline (formout, buf);
    > >       L6:file_close(formout);

    >
    > >but I got the following error message:

    >
    > ># ** Error: C:/Users/Daniele/Desktop/Esercizi/Format_IO.vhd(24):
    > >Subprogram 'write' is ambiguous.

    >
    > >where am I wrong?

    >
    > OK, that one's easy...
    >
    > There are at least eight different versions of "write".
    > The version to write a string looks, to the compiler,
    > exactly the same as the version to write a bit-vector:
    >
    >   write(buf, "1011"); -- String or bit-vector???
    >
    > Hence the "ambiguous" error message.  There are two
    > possible fixes:
    >
    > 1) Type-qualify the string:
    >
    >   write(buf, string'("My message"));
    >
    > 2) Create a specialised version of "write", with a
    > different name, to deal with the very common problem
    > of writing a string message:
    >
    >   procedure WrStr(L: inout line; S: in string) is
    >   begin
    >     write (L, S);  -- No ambiguity; S is of string type
    >   end;
    >
    > Now you can do simply
    >
    >   WrStr(buf, "My message");
    >
    > and all will be well.
    >
    > FOOTNOTE for the nitpickier members of c.l.vhdl:
    > The simple implementation of WrStr, above, is
    > incomplete.  To provide the full facilities of
    > "write", complete with formatting, you need this
    > slightly more complex version:
    >
    >   procedure WrStr
    >     ( L         : inout line
    >     ; S         : in string
    >     ; JUSTIFIED : in SIDE := right
    >     ; FIELD     : in WIDTH := 0
    >     ) is
    >   begin
    >     write(L, S, JUSTIFIED, FIELD);
    >   end;
    >
    > Of course, thanks to the default arguments you can
    > still call it like this if you wish:
    >   WrStr(buf, "message");
    > --
    > Jonathan Bromley, Consultant
    >
    > DOULOS - Developing Design Know-how
    > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
    >
    > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
    > ://www.MYCOMPANY.com
    >
    > The contents of this message may contain personal views which
    > are not the views of Doulos Ltd., unless specifically stated.


    Thank you very much

    now it works properly
    Dek, Apr 23, 2009
    #7
  8. Dek

    Dek Guest

    On 23 Apr, 11:26, Bert_Paris <> wrote:
    > Dek avait prétendu :
    >
    > >        L1:write (buf, "This is an example of formatted I/O");

    >
    > You need to use qualified expressions :
    >        L1:write (buf, string'("This is an example of formatted I/O"));
    >
    > I personnaly use often the trick to concatenate a character.
    > "Hello" & HT becomes automatically a string (it's not ambiguous any
    > more)
    >
    > We teach this in the Doulos course ;-)
    >
    > Bert



    Thank you very much,

    now it works properly, but I didn't how to concatenate a character;
    what should I write?
    Dek, Apr 23, 2009
    #8
  9. Dek

    Dek Guest

    On 23 Apr, 11:26, Bert_Paris <> wrote:
    > Dek avait prétendu :
    >
    > >        L1:write (buf, "This is an example of formatted I/O");

    >
    > You need to use qualified expressions :
    >        L1:write (buf, string'("This is an example of formatted I/O"));
    >
    > I personnaly use often the trick to concatenate a character.
    > "Hello" & HT becomes automatically a string (it's not ambiguous any
    > more)
    >
    > We teach this in the Doulos course ;-)
    >
    > Bert





    Thank you all,

    now it works properly, but I didn't get how to concatenate a
    character;
    what should I write?

    Thanks

    Bye
    Dek, Apr 23, 2009
    #9
  10. Dek

    HT-Lab Guest

    "Dek" <> wrote in message
    news:...
    > Hi everybody,
    >
    > I'm new to VHDL an to this group too; as an exercise I'm trying to
    > import data from several files using package TextIO, but I haven't
    > found yet a good manual or tutorial about it; may you suggest me some?
    >
    > Thanks
    >
    > Bye
    >
    > Dek


    Hi Dek,

    As has been suggested a number of times on this newsgroup you might want to
    check out the VHDL stdio package:

    http://bear.ces.case.edu/VHDL/index.html

    if you know C than this package makes textio a lot easier (at least I think
    it does),

    Hans
    www.ht-lab.com
    HT-Lab, Apr 23, 2009
    #10
  11. Dek

    Bert_Paris Guest

    Dek a utilisé son clavier pour écrire :
    > On 23 Apr, 11:26, Bert_Paris <> wrote:
    >> Dek avait prétendu :
    >>
    >>>        L1:write (buf, "This is an example of formatted I/O");

    >>
    >> You need to use qualified expressions :
    >>        L1:write (buf, string'("This is an example of formatted I/O"));
    >>
    >> I personnaly use often the trick to concatenate a character.
    >> "Hello" & HT becomes automatically a string (it's not ambiguous any
    >> more)
    >>
    >> We teach this in the Doulos course ;-)
    >>
    >> Bert

    >
    >
    >
    >
    > Thank you all,
    >
    > now it works properly, but I didn't get how to concatenate a
    > character;
    > what should I write?
    >
    > Thanks
    >
    > Bye


    "Hello" & HT
    Bert_Paris, Apr 23, 2009
    #11
  12. Dek

    Dek Guest

    On 23 Apr, 14:04, Bert_Paris <> wrote:
    > Dek a utilisé son clavier pour écrire :
    >
    >
    >
    >
    >
    > > On 23 Apr, 11:26, Bert_Paris <> wrote:
    > >> Dek avait prétendu :

    >
    > >>>        L1:write (buf, "This is an example of formatted I/O");

    >
    > >> You need to use qualified expressions :
    > >>        L1:write (buf, string'("This is an example of formatted I/O"));

    >
    > >> I personnaly use often the trick to concatenate a character.
    > >> "Hello" & HT becomes automatically a string (it's not ambiguous any
    > >> more)

    >
    > >> We teach this in the Doulos course ;-)

    >
    > >> Bert

    >
    > > Thank you all,

    >
    > > now it works properly, but I didn't get how to concatenate a
    > > character;
    > > what should I write?

    >
    > > Thanks

    >
    > > Bye

    >
    > "Hello" & HT- Nascondi testo citato
    >
    > - Mostra testo citato -


    Nice trick,
    thanks again
    Dek, Apr 23, 2009
    #12
  13. Dek

    JimLewis Guest

    Hi,
    > 2) Create a specialised version of "write", with a
    > different name, to deal with the very common problem
    > of writing a string message:
    >
    >   procedure WrStr(L: inout line; S: in string) is
    > ...


    In the VHDL-2008 language revision, the following alias
    was added to std.textio:

    alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH];

    You call SWRITE just like Jonanthan's WrStr.

    I have been using some of the supported VHDL-2008
    features in both ModelSim and Aldec. If you have the
    latest versions, I suspect this is in the supported list.

    Cheers,
    Jim
    SynthWorks VHDL Training

    P.S.
    If you are in the US, SynthWorks also covers textio
    and has regularly scheduled classes.
    http://www.synthworks.com
    JimLewis, Apr 23, 2009
    #13
  14. Dek wrote:

    > what I want to do actually is an hardware model using a .txt file for
    > the testbench. I' m trying to read different lines from a single file,
    > and different data from a single line, and writing the same.


    It is quite common for new vhdl testbenchers
    to try to write a text script and interpret it using
    textio rather than learning how to use
    vhdl types and procedures.
    I will decline to elaborate because
    I don't think this is a good idea.

    > Where can I find Doulos VHDL courses?


    http://www.doulos.com/

    -- Mike Treseler
    Mike Treseler, Apr 23, 2009
    #14
  15. Dek

    Dek Guest

    On 23 Apr, 19:19, Mike Treseler <> wrote:
    > Dek wrote:
    > > what I want to do actually is an hardware model using a .txt file for
    > > the testbench. I' m trying to read different lines from a single file,
    > > and different data from a single line, and writing the same.

    >
    > It is quite common for new vhdl testbenchers
    > to try to write a text script and interpret it using
    > textio rather than learning how to use
    > vhdl types and procedures.
    > I will decline to elaborate because
    > I don't think this is a good idea.
    >
    > > Where can I find Doulos VHDL courses?

    >
    > http://www.doulos.com/
    >
    >      -- Mike Treseler



    I think I can't do anything better, because I have to simulate how an
    FPGA would work on data coming from a detector, that are already
    stored in many .txt files.

    Now the problem is that such files are thousands and it takes a lot of
    time to change manually their name in vhdl code. One idea is to use
    Generics, name all data files in a "name.do" file and use "do name.do"
    command. Even in this case, however, I have to name files manually one
    by one. Do you know if there is a way to read all files in a folder
    without nameing them?
    The same problem, unfortunately, is for writing, since for each in-
    file I have to write one out-file.

    Thanks

    Bye
    Dek, Apr 24, 2009
    #15
  16. Dek

    Guest

    On 22 ×פריל, 10:57, Dek <> wrote:
    > Hi everybody,
    >
    > I'm new to VHDL an to this group too; as an exercise I'm trying to
    > import data from several files using package TextIO, but I haven't
    > found yet a good manual or tutorial about it; may you suggest me some?
    >
    > Thanks
    >
    > Bye
    >
    > Dek


    You may see this page as an example for text io usyage.
    ....
    Sometimes simulation are very long, which makes it impossible to
    record waves for the entire simulation. The monitor helps you locate
    those areas, which need debug and waves.
    ....
    http://bknpk.no-ip.biz/AHB_MON/ahb_mon_1.html
    , Apr 24, 2009
    #16
  17. Dek

    KJ Guest


    > I think I can't do anything better, because I have to simulate how an
    > FPGA would work on data coming from a detector, that are already
    > stored in many .txt files.
    >


    One could ask how did those files get created in the first place. Unless
    they were generated from an actual detector, then they were artificially
    generated in the first place. Rather than artificially generating data into
    text files and then figuring out how to read them into a testbench it is
    much more productive to model the detector in the VHDL testbench and totally
    bypass file I/O (which is not really one of VHDL's strengths).

    But I'll assume though that you have to work with file I/O.

    > Now the problem is that such files are thousands and it takes a lot of
    > time to change manually their name in vhdl code. One idea is to use
    > Generics, name all data files in a "name.do" file and use "do name.do"
    > command. Even in this case, however, I have to name files manually one
    > by one.


    Not really. The name.do file can be easily created with a simple directory
    listing command
    (Windows command line "dir /b >name.do"). That's pretty easy to do.

    > Do you know if there is a way to read all files in a folder
    > without nameing them?


    I don't.

    > The same problem, unfortunately, is for writing, since for each in-
    > file I have to write one out-file.
    >

    Once you've read in a line from 'name.do' you've got a unique input file
    name. I would construct a similarly unique output file name by modifying
    the input file name in some fashion (say by appending ".out" to the input
    file name).

    Kevin Jennings
    KJ, Apr 25, 2009
    #17
  18. Dek

    HT-Lab Guest

    "Dek" <> wrote in message
    news:...
    On 23 Apr, 19:19, Mike Treseler <> wrote:
    > Dek wrote:
    > I think I can't do anything better, because I have to simulate how an
    > FPGA would work on data coming from a detector, that are already
    > stored in many .txt files.
    >
    > Now the problem is that such files are thousands and it takes a lot of
    > time to change manually their name in vhdl code. One idea is to use
    > Generics, name all data files in a "name.do" file and use "do name.do"
    > command. Even in this case, however, I have to name files manually one
    > by one. Do you know if there is a way to read all files in a folder
    > without nameing them?


    Look into using Tcl which if fully integrated with Modelsim. To read a
    directory simply use the "glob *" command followed by a "foreach" to handle
    each filename. Other useful Tcl Modelsim commands are force/when and examine
    (see manual),

    Hans
    www.ht-lab.com



    >The same problem, unfortunately, is for writing, since for each in-
    >file I have to write one out-file.
    >
    >Thanks
    >
    >Bye
    HT-Lab, Apr 25, 2009
    #18
  19. Dek

    Dek Guest

    On 25 Apr, 10:01, "HT-Lab" <> wrote:
    > "Dek" <> wrote in message
    >
    > news:...
    > On 23 Apr, 19:19, Mike Treseler <> wrote:
    >
    > > Dek wrote:
    > > I think I can't do anything better, because I have to simulate how an
    > > FPGA would work on data coming from a detector, that are already
    > > stored in many .txt files.

    >
    > > Now the problem is that such files are thousands and it takes a lot of
    > > time to change manually their name in vhdl code. One idea is to use
    > > Generics, name all data files in a "name.do" file and use "do name.do"
    > > command. Even in this case, however, I have to name files manually one
    > > by one. Do you know if there is a way to read all files in a folder
    > > without nameing them?

    >
    > Look into using Tcl which if fully integrated with Modelsim. To read a
    > directory simply use the "glob *" command followed by a "foreach" to handle
    > each filename. Other useful Tcl Modelsim commands are force/when and examine
    > (see manual),
    >
    > Hanswww.ht-lab.com
    >
    >
    >
    > >The same problem, unfortunately, is for writing, since for each in-
    > >file I have to write one out-file.

    >
    > >Thanks

    >
    > >Bye- Nascondi testo citato

    >
    > - Mostra testo citato -


    Thanks all

    I think I'll try first the idea of KJ; since I'm just learning VHDL
    and ModelSim, I'll leave Tcl for the future.

    Thanks again

    Bye

    Dek
    Dek, Apr 27, 2009
    #19
  20. Dek

    Dek Guest

    On 25 Apr, 02:21, "KJ" <> wrote:
    > > I think I can't do anything better, because I have to simulate how an
    > > FPGA would work on data coming from a detector, that are already
    > > stored in many .txt files.

    >
    > One could ask how did those files get created in the first place.  Unless
    > they were generated from an actual detector, then they were artificially
    > generated in the first place.  Rather than artificially generating data into
    > text files and then figuring out how to read them into a testbench it is
    > much more productive to model the detector in the VHDL testbench and totally
    > bypass file I/O (which is not really one of VHDL's strengths).
    >
    > But I'll assume though that you have to work with file I/O.
    >
    > > Now the problem is that such files are thousands and it takes a lot of
    > > time to change manually their name in vhdl code. One idea is to use
    > > Generics, name all data files in a "name.do" file and use "do name.do"
    > > command. Even in this case, however, I have to name files manually one
    > > by one.

    >
    > Not really.  The name.do file can be easily created with a simple directory
    > listing command
    > (Windows command line "dir /b >name.do").  That's pretty easy to do.
    >
    > > Do you know if there is a way to read all files in a folder
    > > without nameing them?

    >
    > I don't.
    >
    > > The same problem, unfortunately, is for writing, since for each in-
    > > file I have to write one out-file.

    >
    > Once you've read in a line from 'name.do' you've got a unique input file
    > name.  I would construct a similarly unique output file name by modifying
    > the input file name in some fashion (say by appending ".out" to the input
    > file name).
    >
    > Kevin Jennings



    Ok, I'll definitively thank this group in my thesis! Your idea seems
    to work, but there is still a little problem:

    the name are of different length! If i do like this:
    -----------------------------------------------
    Architecture...
    Begin
    process
    VARIABLE filename : String (23 downto 1);
    -----------------------------------------------
    it works until it find a filename of lenght different from 23.

    I tried to do something like this:
    VARIABLE filename : String;
    or
    VARIABLE filename : String (natural range<>);
    but I always get an error message.
    Have any suggestion?

    Thanks

    Dek
    Dek, Apr 28, 2009
    #20
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