The definition of combinatorial process?

[Weng Tianxiang]

The following topic may be one of the longest debate in vhdl group:
http://groups.google.com/group/comp...de3fe8ea3eec9ad?hl=en&q=combinatorial&lnk=ol&

The debute focus later turns to which is best way to use one
sequential process or two combinarotial process and sequential
process.

The most important and strange thing is that I cannot even find the
word "combinarotial" in VHDL-2002 specification.

I want to grammarly define a combinatorial process which cannot have a
clock statement in one of my thinking.

process_statement_part ::=
{ sequential_statement }

sequential_statement ::=
wait_statement
| assertion_statement
| report_statement
| signal_assignment_statement
| variable_assignment_statement
| procedure_call_statement
| if_statement
| case_statement
| loop_statement
| next_statement
| exit_statement
| return_statement
| null_statement

combinatorial_process_statement_part ::=
{ combinatorial_sequential_statement }

combinatorial_sequential_statement ::=
assertion_statement -- wait_statement is deleted here !!!
| report_statement
| signal_assignment_statement
| variable_assignment_statement
| procedure_call_statement
| if_statement
| case_statement
| loop_statement
| next_statement
| exit_statement
| return_statement
| null_statement

Weng

 

[KJ]

The debute focus later turns to which is best way to use one
sequential process or two combinarotial process and sequential
process.

The most important and strange thing is that I cannot even find the
word "combinarotial" in VHDL-2002 specification.

Why do you consider it strange? The word 'clock' is not defined in the specification either because it is not relevant to the language definition.

I want to grammarly define a combinatorial process which cannot have a
clock statement in one of my thinking.

A 'clock' is generally considered to be a signal where one (or both) edges cause another signal(s) to be sampled at the desired edge. The VHDL language allows for the description of such a hardware sampling mechanism to be inferred because it defines the signal attribute called 'event. The definition of 'event enables the description of a 'clock' signal but it can be used for other purposes as well that have nothing at all to do with a 'clock'.

Given that background, one could try to define a combinatorial process as being one that does not use the 'event attribute...but that would be both incomplete as well as too much. It is 'incomplete' in the sense that one could use other defined attributes to equivalently describe the sampling mechanism. It is 'too much' in that just because a process uses 'event, does not imply that the signal in question is used to sample anything else (for example in a testbench).

Copyright 2012
Kevin Jennings

 

[Guest]

A 'clock' is generally considered to be a signal where one (or both) edges cause another signal(s) to be sampled at the desired edge. The VHDL language allows for the description of such a hardware sampling mechanism to be inferred because it defines the signal attribute called 'event. The definition of 'event enables the description of a 'clock' signal but it can be used for other purposes as well that have nothing at all to do with a 'clock'.

Given that background, one could try to define a combinatorial process as being one that does not use the 'event attribute...but that would be both incomplete as well as too much. It is 'incomplete' in the sense that one could use other defined attributes to equivalently describe the sampling mechanism. It is 'too much' in that just because a process uses 'event, does not imply that the signal in question is used to sample anything else (for example in a testbench).

You don't need 'event to describe a "clocked" process; a sensitivity
list does the same thing for you. This means that you can define a
"clocked process" with a concurrent signal assignment, because of the
equivalent process. I haven't checked myself, but I think this works
in some/many synthesisers.

Weng: VHDL has no concept of "clocked" and "combinatorial". Signals
just change at defined times. This has to be true, when you consider
that even real F/Fs are just combinatorial circuits with feedback.
What does "clocked" actually mean? The distinction between "clocked"
and "combinatorial" is made heuristically, by *synthesisers*, to find
out which primitives to use.

Copyright 2012

You're kdding, right?

 

[KJ]

You don't need 'event to describe a "clocked" process; a sensitivity
list does the same thing for you. This means that you can define a
"clocked process" with a concurrent signal assignment, because of the
equivalent process. I haven't checked myself, but I think this works
in some/many synthesisers.

A concurrent assignment can be used to define a clocked signal, but it would have to use either 'event or some other similar signal attribute that fires only on a signal change. The form would be

y <= x when rising_edge(clock);

This is recognized by Quartus and Synplify, haven't checked Xilinx.

As I mentioned, prohibiting 'event would not be sufficient to conclude thata process is 'combinatorial' and you point out another possible form whichwould be

process(clock)
begin
if (clock = '1') then
y <= x;
end if;
end process;

No commercial synthesis tool will infer a flip flop from the above because it will warn about an incomplete sensitivity list and add signals to the sensitivity list instead. But from the definition of the language the above does describe a flip flop, only the synthesis tools non-compliance to the language standard makes it synthesize to something else.

You're kdding, right?

Nope, but I can't disclose the reason.
Copyright 2012
Kevin Jennings

 

[Paul Uiterlinden]

You don't need 'event to describe a "clocked" process; a sensitivity
list does the same thing for you. This means that you can define a
"clocked process" with a concurrent signal assignment, because of the
equivalent process. I haven't checked myself, but I think this works
in some/many synthesisers.

Without 'event (or rising_edge)?

q <= d when clk = '1';

Think again: it is a latch.

The equivalent process is:

process(clk, d)
begin
if clk = '1' then
q <= d;
end if;
end process;

Yup: d is in the sensitivity list.

 

[Weng Tianxiang]

Without 'event (or rising_edge)?

q <= d when clk = '1';

Think again: it is a latch.

The equivalent process is:

process(clk, d)
begin
if clk = '1' then
q <= d;
end if;
end process;

Yup: d is in the sensitivity list.

Actually I want to create something new in HDL, a new type of process, that leads to the problem: the concept of a concurrent combinatorial process:
1. The new process is a concurrent process as other processes are.
2. In the new process, no traditional clock statement, explicit or implicit, is allowed.
3. In the new process all sequential statements, excluding wait statement, are allowed.

Someone may ask that what "a traditional clock statement" means? All those who write logic programming in VHDL know it, but there is never a definition of it in VHDL language. I would like to have someone to fill the gap.

Is it clear enough now?

1. " if rising_edge(clk) then": the situation will be excluded by note 2, not by grammar.

2. "wait for 1 ns;": wait statement is prohibited in the grammar.

I don't see any conflicts now.

I appreciate the SystemVerilog grammar by declaring three types of processes explicitly:
a. always_comb;
b. always_latch;
c. always_ff.

No any ambiguity is generated in any situations.

Thank you for your discussion.

Weng

 

[Jim]

Have you seen VHDL-2008, process(all):

process(all)
begin
... -- combinational logic
end process ;


IEEE std 1076 does not define combinational, however,
the deprecated standard, IEEE 1076.6 does.

 

[Weng Tianxiang]

Have you seen VHDL-2008, process(all):

process(all)
begin
... -- combinational logic
end process ;


IEEE std 1076 does not define combinational, however,
the deprecated standard, IEEE 1076.6 does.

Hi,
Could you send me a copy of IEEE 1076.6? wtxwtx @ gmail . com

Weng

 

[Guest]

Without 'event (or rising_edge)?

q <= d when clk = '1';

Think again: it is a latch.

That's *your* example; not mine. KJ stated that

The VHDL language allows for the description of such a hardware sampling
mechanism to be inferred because it defines the signal attribute called 'event
and

It is 'incomplete' in the sense that one could use other defined attributes
to equivalently describe the sampling mechanism

My response was that you don't need 'event (or any other attribute) to
define a "register" mechanism. There is an obvious process model that
doesn't use 'event; you can use a concurrent procedure which doesn't
have the data input in its parameter list; you can use guarded
signals/regs. And, fundamentally, you can just code up a flip/flop
model using combinatorial feedback, or master/slave latches, or
whatever, using no attributes. You might even be able to do it by
delta-delaying a clock signal and using the overlap for sampling.

Besides, this all irrelevant to the OP; the attempt to define
"registered" has just added to the OP's confusion.

 

[Paul Uiterlinden]

That's *your* example; not mine.

That's correct. I never said is was your example.

The only point I wanted to make clear is that you cannot describe a
flip-flop with just a concurrent signal assignment, because "a sensitivity
list does the same thing for you". The point I was trying to make is that
there is no way to keep d out of the sensitivity list of the equivalent
process when using a concurrent signal assignment.

 

[Andy]

Weng, That is a copyrighted standard, for which you must pay IEEE or
one of their distributors (IHS, et al).

Jim, I was not aware that 1076.6 was deprecated. When/why did that
happen? Did/will something else replace it? The 2004 edition is quite
good at describing the coded behavior necessary to infer a register
and/or latch. Combinatorial processes are assumed to be everything
else.

Andy

 

[Gabor]

The following topic may be one of the longest debate in vhdl group:
http://groups.google.com/group/comp...de3fe8ea3eec9ad?hl=en&q=combinatorial&lnk=ol&

The debute focus later turns to which is best way to use one
sequential process or two combinarotial process and sequential
process.

The most important and strange thing is that I cannot even find the
word "combinarotial" in VHDL-2002 specification.

I want to grammarly define a combinatorial process which cannot have a
clock statement in one of my thinking.

process_statement_part ::=
{ sequential_statement }

sequential_statement ::=
wait_statement
| assertion_statement
| report_statement
| signal_assignment_statement
| variable_assignment_statement
| procedure_call_statement
| if_statement
| case_statement
| loop_statement
| next_statement
| exit_statement
| return_statement
| null_statement

combinatorial_process_statement_part ::=
{ combinatorial_sequential_statement }

combinatorial_sequential_statement ::=
assertion_statement -- wait_statement is deleted here !!!
| report_statement
| signal_assignment_statement
| variable_assignment_statement
| procedure_call_statement
| if_statement
| case_statement
| loop_statement
| next_statement
| exit_statement
| return_statement
| null_statement

Weng

The traditional meaning of "combinatorial" is that the outputs only
depend on the current state of the inputs. i.e. there can be no
saved state within the process. This not only includes constructs
such as edge dependencies or waits, but also any sort of feedback
from the process outputs or internal signals / variables.

-- Gabor

 

[Gabor]

The traditional meaning of "combinatorial" is that the outputs only
depend on the current state of the inputs. i.e. there can be no
saved state within the process. This not only includes constructs
such as edge dependencies or waits, but also any sort of feedback
from the process outputs or internal signals / variables.

-- Gabor

I forgot to add that feedback in the process isn't always obvious
just by looking at the RHS of the equations. Implicit feedback
occurs when you have incomplete state coverage, as in the latch
example. This makes it a bit tougher to prevent sequential logic
from being inferred just by excluding certain types of statements.

-- Gabor

 

[Jim]

Hi Weng,
You can buy a copy here:
http://www.techstreet.com/standards/ieee/1076_6_2004?product_id=1270145

Best,
Jim

 

[Jim]

Jim, I was not aware that 1076.6 was deprecated.
It was due for revision in 2009. Since no one stepped up to lead the group, DASC deprecated both it and the corresponding Verilog one.

Largely users did not pay any attention to it and as a result vendors did not completely implement it. It would be nice to reform a group and revise it, however, someone would need to be willing to do the work. They would also need to get the vendors involved. With FPGAs a diverse set of tools inthe FPGA market, perhaps it can get done. At least for attributes, it really needs to get done.