the "Don't care" value

[Day_1]

Hello,

I'm a VHDL neophyte, so please excuse my very elementary question :tounge:
I wanted to make sure that the " - " Don't care value means that we are indifferent to the value of the signal so it is used only during the allocation of that signal.

 

[jeppe]

Hi -
Indeed is Don't care only for input, however can't you be sure that your synthesize / simulation tool will be able to handle this value correctly.