the "Don't care" value

Discussion in 'VHDL' started by Day_1, Feb 12, 2012.

  1. Day_1

    Day_1

    Joined:
    Feb 12, 2012
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    Hello,

    I'm a VHDL neophyte, so please excuse my very elementary question :tounge:
    I wanted to make sure that the " - " Don't care value means that we are indifferent to the value of the signal so it is used only during the allocation of that signal.
    Day_1, Feb 12, 2012
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  2. Day_1

    jeppe

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    Mar 10, 2008
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    Hi -
    Indeed is Don't care only for input, however can't you be sure that your synthesize / simulation tool will be able to handle this value correctly.
    jeppe, Feb 14, 2012
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