The first ASIC designed with MyHDL

Discussion in 'VHDL' started by Jan Decaluwe, Mar 16, 2010.

  1. Jan Decaluwe

    Jan Decaluwe Guest

    I am proud to report on the first ASIC product
    designed with MyHDL. (afaik)

    In particular, read how MyHDL's conversion capabilities
    to both Verilog and VHDL were very useful in the project.

    Also read about test-driven hardware development,
    and idea whose time has come!

    http://www.jandecaluwe.com/hdldesign/digmac.html

    --
    Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com
    Jan Decaluwe, Mar 16, 2010
    #1
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  2. Jan Decaluwe

    d_s_klein Guest

    On Mar 16, 3:15 am, Jan Decaluwe <> wrote:
    >
    > Also read about test-driven hardware development,
    > and idea whose time has come!
    >


    From the web site mentioned:
    "the verification-related innovations that are happening in the
    software development world are seemingly being ignored by the hardware
    design community"

    In my experience, exactly the opposite is true. It costs 30 seconds
    to re-compile a module, and it costs USD 1,200,000.00 to get a new set
    of masks. I see the software community getting lazier and lazier, and
    the hardware community getting smarter and smarter.

    If -any- chip had the bug to feature ratio of the software I see
    advertised on TV, the company would sell zero, get entangled in
    lawsuits, and be broke within a week.

    RK
    d_s_klein, Mar 16, 2010
    #2
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  3. Jan Decaluwe

    perich Guest

    Hello Jan,

    First of all, congratulations with this result!

    I have only recently become acquainted with myHDL and it looks very
    nice.
    Specifically, I like myHDL's conversion capabilities and the
    possibility of writing testbenches in python.

    I have a question on myHDL's conversion capabilities:
    When I use a 'elif some_condition:' statement and try to translate it
    to VHDL I get the following error:

    myhdl.ConversionError: in file regp2p.py, line 15:
    no else test

    With the toVerilog function the translation works fine.

    Is a 'elif some_condition:' statement treated differently by the
    toVHDL function (than by the toVerilog function) or is a 'elif
    some_condition:' statement in myHDL something other than a 'else: if
    some_condition:' statement?

    I attached a small example at the end of this post (a posedge
    sensitive register with an asynchronous clear and an enable input).

    Thanks,
    Patrick

    from myhdl import *

    def regp2p(
    clr,
    clk,
    en,
    pin,
    pout,
    width
    ):

    intreg = Signal(intbv(0)[width:])

    @always(clk.posedge, clr.posedge)
    def register_p2p():
    if clr:
    intreg.next = 0
    # This works with toVerilog but not with toVHDL
    elif en:
    intreg.next = pin
    # This works with both toVerilog and toVHDL
    # else:
    # if en:
    # intreg.next = pin

    @always_comb
    def outputs():
    pout.next = intreg

    return register_p2p, outputs

    width = int(8)
    clr = Signal(bool(0))
    clk = Signal(bool(0))
    en = Signal(bool(0))
    pin = Signal(intbv(0)[width:])
    pout = Signal(intbv(0)[width:])

    def main():
    toVerilog.name = 'regp2p'
    toVerilog(
    regp2p,
    clr = clr,
    clk = clk,
    en = en,
    pin = pin,
    pout = pout,
    width = width
    )
    toVHDL(
    regp2p,
    clr = clr,
    clk = clk,
    en = en,
    pin = pin,
    pout = pout,
    width = width
    )

    if __name__ == '__main__':
    main()
    perich, Mar 26, 2010
    #3
  4. Jan Decaluwe

    Jan Decaluwe Guest

    On Mar 26, 8:44 pm, perich <> wrote:
    > Hello Jan,
    >
    > First of all, congratulations with this result!
    >
    > I have only recently become acquainted with myHDL and it looks very
    > nice.
    > Specifically, I like myHDL's conversion capabilities and the
    > possibility of writing testbenches in python.
    >
    > I have a question on myHDL's conversion capabilities:
    > When I use a 'elif some_condition:' statement and try to translate it
    > to VHDL I get the following error:
    >
    > myhdl.ConversionError: in file regp2p.py, line 15:
    >     no else test
    >
    > With the toVerilog function the translation works fine.



    In MyHDL and Verilog you can specify a posedge in a
    sensivity list, but in VHDL you can't, so the convertor
    has to do some additional transformations. I'll
    answer in more detail on the MyHDL mailing list, to
    avoid irritations here :)

    --
    Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com
    Jan Decaluwe, Mar 29, 2010
    #4
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