The VHDL coding question

[LiamChang]

Hi
I am an verilog engineer in Taiwan IC design House.
I got a IP written by VHDL form Qualcomm

But, I dont understand the meaning about below declaration
First Question:
" B : IN vector_of_std_logic_vector8(0 TO 63); -- ufix8_En8 [64] "
the vector_of_stb_logic8(0 TO 63) means ??
What's the different form STD_LOGIC_VECTOR (63 downto 0) ??

Can I replace them with STD_LOGIC_VECTOR..... declaration ??

Thanks very much !!

 

[JohnDuq]

In

http://www.ece.uah.edu/~gaede/cpe526/vhdl_src/vital2.2b/prmtvs_p.vhd

I see the following definitions:

-- ----------------------------------------------------------------------------
-- Type and Subtype Declarations
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- All of these SUBTYPE declarations are defined in the VITAL_TIMING package
-- but are repeated here for ease of readability. WARNING: Do Not Uncomment if
-- you plan to USE both packages as this may render the SUBTYPE declarations
-- invisible to the user due to mutual hiding.
--
-- SUBTYPE std_logic_vector2 IS std_logic_vector(1 DOWNTO 0);
-- SUBTYPE std_logic_vector3 IS std_logic_vector(2 DOWNTO 0);
-- SUBTYPE std_logic_vector4 IS std_logic_vector(3 DOWNTO 0);
-- SUBTYPE std_logic_vector8 IS std_logic_vector(7 DOWNTO 0);
-- ----------------------------------------------------------------------------

This is ASIC specific code, so my belief is that ...vector8 is used to define registers on a byte-wide basis.

You'll need to dig into the VITAL_TIMING package for more definition.

John