Time Array

Discussion in 'VHDL' started by ALuPin@web.de, Nov 29, 2005.

  1. Guest

    Hi,

    I define the following type and a signal of that type:

    TYPE type_t_time_vector IS ARRAY (34 DOWNTO 0) OF TIME := (3 ns, 3.5
    ns, 4 ns, 4.5 ns, 5 ns, 5.5 ns, 6 ns, 6.5 ns, 7 ns, 7.5 ns, 8 ns, 8.5
    ns, 9 ns, 9.5 ns, 10 ns, 10.5 ns,
    11 ns, 11.5 ns, 12 ns, 12.5 ns, 13 ns, 13.5 ns, 14 ns, 14.5 ns,
    15 ns, 15.5 ns, 16 ns, 16.5 ns, 17 ns, 17.5 ns, 18 ns, 18.5 ns,
    19 ns, 19.5 ns, 20 ns);

    SIGNAL t_time_vector : type_t_time_vector;

    When compiling my VHDL testbench I get the followin error message:


    ** Error:
    h:/eda/lattice/dvi_pc_top_ispLEVER51/complex_simu/fifo_vs_ddr_ip/tb_fifo_vs_ddr_ip.vhd(168):
    near ":=": expecting: ';'
    # ** Error: D:/Programme/Lattice/ISPLever51/modelsim/win32loem/vcom
    failed.

    Line 168 marks the line where the type declaration begins

    Any idea what is wrong here ?

    Rgds
    André
     
    , Nov 29, 2005
    #1
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  2. Ajeetha Guest

    Andre,
    Move the value initialization to the signal definition line than
    to the TYPE itself. I tried on Simli, it works just fine.

    HTH
    Ajeetha
    www.noveldv.com
     
    Ajeetha, Nov 29, 2005
    #2
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  3. Guest

    Hi Ajeetha,

    yes it works, thank you very much.

    Rgds
    André
     
    , Nov 30, 2005
    #3
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