Time delay

Discussion in 'VHDL' started by Aliki, Sep 22, 2004.

  1. Aliki

    Aliki Guest

    Can anybody tell me how can I make a module within a design, to start
    getting its input with a little delay (for instance a few nanoseconds.
    I've tried the "after X ns" with no success.
    Thank you in advance.
     
    Aliki, Sep 22, 2004
    #1
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  2. On Wed, 22 Sep 2004 09:48:48 -0400, "Aliki" <aliki@> wrote:

    >Can anybody tell me how can I make a module within a design, to start
    >getting its input with a little delay (for instance a few nanoseconds.
    >I've tried the "after X ns" with no success.
    >Thank you in advance.


    "sig <= <whatever> after X ns;" will give you an inertial delay.

    Try "sig <= transport <whatever> after X ns;" instead.


    OTOH, you may have your simulator time resolution set too low
    (coarse). Time delays less than the resolution get rounded down to
    zero.

    Regards,
    Allan
     
    Allan Herriman, Sep 22, 2004
    #2
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  3. Aliki wrote:

    > Can anybody tell me how can I make a module within a design, to start
    > getting its input with a little delay (for instance a few nanoseconds.
    > I've tried the "after X ns" with no success.


    Consider using a synchronous design with a clock input.
    This allows you to think about logic description
    while the place and route worries about adding
    up gate delays to meet the fmax spec.

    -- Mike Treseler
     
    Mike Treseler, Sep 22, 2004
    #3
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