time set up

Discussion in 'VHDL' started by Andres, Jan 23, 2004.

  1. Andres

    Andres Guest

    Hi everyone!!!

    I'm actually doing my thesis wich consists in implementing an algorithm in a
    FPGA. I've done the desing and works right in all the simulations except in
    Post Place and Route simulation. In fact, the results are right but betwen
    every 2 data appears valid data that shouldn't appear. What should I do? How
    can I fix it ? Should I have to manipulate the set up time of the elements ?
    How can I do that?

    I'm using ISE 5.1 and ModelSim XE II v5.6e.

    Thanks
     
    Andres, Jan 23, 2004
    #1
    1. Advertising

  2. Andres wrote:
    > Hi everyone!!!
    >
    > I'm actually doing my thesis wich consists in implementing an algorithm in a
    > FPGA. I've done the desing and works right in all the simulations except in
    > Post Place and Route simulation. In fact, the results are right but betwen
    > every 2 data appears valid data that shouldn't appear.


    What do you see on the functional sim then? zeros? 'Z's ?
    What do want to see?

    > What should I do? How can I fix it ?


    Watch waves, trace code, edit code, repeat


    -- Mike Treseler
     
    Mike Treseler, Jan 23, 2004
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. engsol
    Replies:
    2
    Views:
    995
    Dan Bishop
    Jan 26, 2004
  2. Replies:
    8
    Views:
    511
    Magnus Lycka
    Aug 5, 2005
  3. flamesrock
    Replies:
    8
    Views:
    553
    Hendrik van Rooyen
    Nov 24, 2006
  4. Ben
    Replies:
    2
    Views:
    403
  5. Phil Powell
    Replies:
    2
    Views:
    242
    Grant Wagner
    Sep 5, 2003
Loading...

Share This Page