timing constraint syntax/fpga editor info

[Serkan]

What is the syntax of this below constraint? I am using xilinx 11.4,
spartan 6, and VHDL

I have a signal say "a" that goes to 2 different "obufds". The delay
between this "a" signal to the pins/pads are 4.8 ns and 2.8ns. Can I
have a constraint that these 4,8 and 2,8 ns delays are smaller like 1
ns and close to each other.

Extra information is below if needed.




=============================
input component
comp "a", site "SLICE_X1Y61", type = SLICEX
=============================

=============================
output component 1
comp "a_p_1", site "B16", bonded type = IOBM, pad name = PAD65,
pin name = B16
=============================

=============================
output component 2
comp "a_p_2", site "B6", bonded type = IOBM, pad name = PAD15, pin
name = B6
=============================

 

[Serkan]

Ok I guess I found the solution. I need to create 2 a signals and use
the syntax below.
By the way 2.160ns is the minumum delay for spartan6slx16 or I am
doing something wrong.
NET "a_1" MAXDELAY = 2 ns;
NET "a_2" MAXDELAY = 2 ns;
==========================================================

Now I have a smaller question: How can I have both a_1 and a_2 in my
design.
xilinx xst eliminates one of these and I have a problem with keep
signal.

a_b_r_process : process (reset_n, clk_50mhz)
begin

if (reset_n = '0') then

a_1 <= '0';
a_2 <= '0';

elsif (clk_48mhz'event and clk_48mhz = '0') then

a_1 <= a;
a_2 <= a;

end if;

end process;


best regards
Serkan

 

[Serkan]

I found the solution on the forums
Please ignore the post.

serkan