Timing constraints in an FPGA

Discussion in 'VHDL' started by boysr2003, Nov 27, 2006.

  1. boysr2003

    boysr2003

    Joined:
    Jul 27, 2006
    Messages:
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    how to meet timing constraints in an FPGA

    Hi, my name is Yassir Boukhriss. I have succesfully integrated a system generator design into a top level code of a digital receiver. The simulink system period is a fraction of the periods of all the blocks in the system generator design. In fact, it's the gcd of all those periods. I had to make it a fraction of those periods to meet the time constraint of the design as a whole. Now, the sample clock in the sys gen is slower by the same factor. Does anyone know if there is another way to match the periods and still meet timing constraints?
     
    Last edited: Dec 7, 2006
    boysr2003, Nov 27, 2006
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