Timing Diagram to HDL Translation

Discussion in 'VHDL' started by Kieran Francisco, Sep 8, 2003.

  1. Hello,

    I am looking for a Tool that I can generate VHDL and/or Verilog
    directly from a timing diagram. I have a bus system in my design that
    is common to many IP blocks and its currently specified as a series of
    read and write bus cycles. I would like to enter these bus cycle
    timings and generate HDL directly from them. Anyone have any good
    ideas.

    Thanks, Kieran.
    Kieran Francisco, Sep 8, 2003
    #1
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  2. Kieran Francisco

    Phil Tomson Guest

    In article <>,
    Kieran Francisco <> wrote:
    >Hello,
    >
    >I am looking for a Tool that I can generate VHDL and/or Verilog
    >directly from a timing diagram. I have a bus system in my design that
    >is common to many IP blocks and its currently specified as a series of
    >read and write bus cycles. I would like to enter these bus cycle
    >timings and generate HDL directly from them. Anyone have any good
    >ideas.
    >
    >Thanks, Kieran.



    Interesting idea. So, if I understand correctly, you would want to
    generate a state machine from a timing diagram and then generate an HDL
    of the state machine. Is that what you're proposing?

    Phil
    Phil Tomson, Sep 8, 2003
    #2
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  3. Kieran Francisco

    Jim Wu Guest

    Take a look at http://www.timingdesigner.com/timingdesigner.asp .

    Jim Wu

    http://www.geocities.com/jimwu88/chips


    "Kieran Francisco" <> wrote in message
    news:...
    > Hello,
    >
    > I am looking for a Tool that I can generate VHDL and/or Verilog
    > directly from a timing diagram. I have a bus system in my design that
    > is common to many IP blocks and its currently specified as a series of
    > read and write bus cycles. I would like to enter these bus cycle
    > timings and generate HDL directly from them. Anyone have any good
    > ideas.
    >
    > Thanks, Kieran.
    Jim Wu, Sep 9, 2003
    #3
  4. Kieran,

    I don't believe timing diagrams can completely specify bus interface.
    They may define some functional constraints, but this will be only
    partial design specification (I even dont mention missed specification
    for "backdoor" side of bus interface). However, partial specification
    still may be useful for automatic generation of verification
    constraints in OVL, OVA, Specman or PSL(Sugar) format. For this
    purpose, you may try TestBencher Pro from SynaptiCAD (If you'll decide
    to evaluate this tool, it would be interesting to get your comments
    about it).

    Regards,
    Alexander Gnusin
    www.TCLforEDA.net
    Alexander Gnusin, Sep 9, 2003
    #4
  5. Our WaveFormer Pro and TestBencher Pro products both have the capability
    to do this to varying degrees. You can find out more at our web site:

    http://www.syncad.com

    best regards,

    Dan Notestein
    SynaptiCAD

    (Kieran Francisco) wrote in
    news::

    > Hello,
    >
    > I am looking for a Tool that I can generate VHDL and/or Verilog
    > directly from a timing diagram. I have a bus system in my design that
    > is common to many IP blocks and its currently specified as a series of
    > read and write bus cycles. I would like to enter these bus cycle
    > timings and generate HDL directly from them. Anyone have any good
    > ideas.
    >
    > Thanks, Kieran.
    Dan Notestein, Sep 10, 2003
    #5
  6. Kieran Francisco

    Paul Chaffey Guest

    Dan Notestein <> wrote in message news:<Xns93F1E20AE3021dansyncadcom@63.223.5.101>...
    > Our WaveFormer Pro and TestBencher Pro products both have the capability
    > to do this to varying degrees. You can find out more at our web site:
    >
    > http://www.syncad.com
    >
    > best regards,
    >
    > Dan Notestein
    > SynaptiCAD
    >
    > (Kieran Francisco) wrote in
    > news::
    >
    > > Hello,
    > >
    > > I am looking for a Tool that I can generate VHDL and/or Verilog
    > > directly from a timing diagram. I have a bus system in my design that
    > > is common to many IP blocks and its currently specified as a series of
    > > read and write bus cycles. I would like to enter these bus cycle
    > > timings and generate HDL directly from them. Anyone have any good
    > > ideas.
    > >
    > > Thanks, Kieran.


    Hi Kieran,

    you can try our products - TimingTool or TimingTool Lite.

    The TimingTool Lite is our free to use online java applet which allows
    users to enter and edit timing diagrams. There are also translators
    that supply full VHDL and Verilog outputs from the timing diagrams.

    The full product, TimingTool has many more features that may be useful
    to you if you are connecting many IP blocks together. This is supplied
    as a download which is installed on your local machine (unlike
    TimingTool Lite). Some of the extra features include relationships
    between edges, parameter tables, a macro language, and excellent
    export capabilities (eg. straight to HTML). Also VHDL and Verilog
    exports are supplied as with the TimingTool Lite product.

    TimingTool can be found at: www.timingtool.com

    Hope this helps,

    Paul.
    Paul Chaffey, Sep 10, 2003
    #6
  7. Dan Notestein <> wrote in message news:<Xns93F1E20AE3021dansyncadcom@63.223.5.101>...
    > Our WaveFormer Pro and TestBencher Pro products both have the capability
    > to do this to varying degrees. You can find out more at our web site:
    >
    > http://www.syncad.com
    >
    > best regards,
    >
    > Dan Notestein
    > SynaptiCAD
    >
    > (Kieran Francisco) wrote in
    > news::
    >
    > > Hello,
    > >
    > > I am looking for a Tool that I can generate VHDL and/or Verilog
    > > directly from a timing diagram. I have a bus system in my design that
    > > is common to many IP blocks and its currently specified as a series of
    > > read and write bus cycles. I would like to enter these bus cycle
    > > timings and generate HDL directly from them. Anyone have any good
    > > ideas.
    > >
    > > Thanks, Kieran.



    Thank you for all your replies to my posting.

    I will try out your recommendations and let you know how I get on.

    Kieran
    Kieran Francisco, Sep 10, 2003
    #7
  8. Kieran Francisco

    VhdlCohen Guest

    >> > I am looking for a Tool that I can generate VHDL and/or Verilog
    >> > directly from a timing diagram. I have a bus system in my design that
    >> > is common to many IP blocks and its currently specified as a series of
    >> > read and write bus cycles. I would like to enter these bus cycle
    >> > timings and generate HDL directly from them. Anyone have any good
    >> > ideas.


    I am questioning the whole premise on the need to generate HDL from
    a timing diagram for TB designs. I personally prefer"
    1. A transaction-based approach (see my site under models, veriflang.pdf
    Document: Transaction-Based Verification in HDL) where the transator (or
    client) makes high level transaction requests, and the server provides the
    low-levl interfaces to the DUT. It is not difficult to code a server to do
    READs, WRITEs, DMA, IDLE, etc. classes of cyles. If that is difficult, then
    you don't understand the design.

    2. I also encourge the use of PSL to perform white-box verification for
    simulation or formal verification.

    ----------------------------------------------------------------------------
    Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
    http://www.vhdlcohen.com/
    Author of following textbooks:
    * Using PSL/SUGAR with Verilog and VHDL
    Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
    * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
    0-9705394-2-8
    * Component Design by Example ", 2001 isbn 0-9705394-0-1
    * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
    * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
    ------------------------------------------------------------------------------
    VhdlCohen, Sep 10, 2003
    #8
  9. Kieran Francisco

    Steve Remme Guest

    You didn't mention if you needed a free tool....if not, an excellent tool
    for doing this is Quickbench from Forte Design Systems. It's easy to use and
    very powerful (you can do things like pause a timing diagram, parameterize
    it, etc.).

    Being primarily a hardware designer, timing diagrams are a common form of
    thinking/explaining for me. I used this in my last job to do verification of
    some IP we were developing for a customer and it was the best verification
    environment I have used.


    "Kieran Francisco" <> wrote in message
    news:...
    > Hello,
    >
    > I am looking for a Tool that I can generate VHDL and/or Verilog
    > directly from a timing diagram. I have a bus system in my design that
    > is common to many IP blocks and its currently specified as a series of
    > read and write bus cycles. I would like to enter these bus cycle
    > timings and generate HDL directly from them. Anyone have any good
    > ideas.
    >
    > Thanks, Kieran.
    >
    Steve Remme, Sep 17, 2003
    #9
  10. Kieran Francisco

    VhdlCohen Guest

    >Being primarily a hardware designer, timing diagrams are a common form of
    >thinking/explaining for me. I used this in my last job to do verification of
    >some IP we were developing for a customer and it was the best verification
    >environment I have used.
    >

    Thin PSL Property Specification Language as Assertion-Based Verification (ABV)
    is really coming into real play for verification.
    .... ABV (like PSL) is to verification as
    RTL is to synthesis .......

    ----------------------------------------------------------------------------
    Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
    http://www.vhdlcohen.com/
    Author of following textbooks:
    * Using PSL/SUGAR with Verilog and VHDL
    Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
    * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
    0-9705394-2-8
    * Component Design by Example ", 2001 isbn 0-9705394-0-1
    * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
    * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
    ------------------------------------------------------------------------------
    VhdlCohen, Sep 17, 2003
    #10
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