Timing issues !!! help help!

Discussion in 'VHDL' started by jaquesgrobler, May 8, 2008.

  1. jaquesgrobler

    jaquesgrobler

    Joined:
    May 8, 2008
    Messages:
    1
    Hola.... okay i'm having a really frustrating problem with timing and I'm running out of time. I'm designing a digital filter for an FPGA, but there are some hicups.

    Basically, the filtering process contains a state machine with 20 states that all follow in straight forward sequence. I make use of megafunction multipliers and adders (LPM_MUL & LPM_ADD). One state will have one multiplication operation. then the output will be fed into an adder in the next state.

    The problem im sitting with is that when i do a functional simulation, the results are correct. however, when i do a timing analysis, the values are incorrect. So I assume it's a timing related problem. The only timing related warning I have is :

    Warning: 31 (of 3893) connections in the design require a large routing delay to achieve hold requirements. Please check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks.

    What exactly does this mean? How do I go about improving this. I'm stil a bit of a beginner with this language.

    The other thing that I think might have a hand in the problem, is this:

    Warning: Latch \p2:Temp_mem[1][0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal present_state.s10


    there are more than one of these. Could they be causing the delays or timing errors? I've seen some other posts on this topic but still don't really grasp how I am suppose to fix it. The code in state S10 looks like this:

    next_state <= S11;
    stop_filter <= '0';
    Temp_mem(Temp_point) := add_output2;
    mul_A1 <= Temp_mem(Temp_point);
    mul_B1 <= COEFB(0);
    shifted_answer1 := mul_ans1 (31 downto 8 );


    next_state is obviously the next state.
    stop_filter is a flag that is turned on later when the sample is filtered.
    Temp_mem (Temp_point) is an array of the following:

    type wrap_memory is
    array(0 to 4) of std_logic_vector (23 downto 0);


    and is used to store 5 values.
    add_output2 is the output from state S9's addition operation.
    Temp_point is just an integer that works like an array index.
    mul_A1 and mul_B1 are the inputs to a multiplier.
    COEFB (0) is a constant value.
    mul_ans1 is the ouput from the multiplier and shifted_answer1 is a valiable it is stored in and carried over in to the next state.

    Any help at all would be appreciated. Basically i need to know if the latch's unsafe behaviour is responsible and how the hell to fix it.

    Thanks to anyone who responds
    Peace
    jaquesgrobler, May 8, 2008
    #1
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