Timing Question

Discussion in 'VHDL' started by Ardni, Oct 28, 2008.

  1. Ardni

    Ardni

    Joined:
    Jul 8, 2008
    Messages:
    23
    Hi,
    I am doing a timing simulation using Modelsim PE 6.2d of a design on an Altera 10Ke device. A Tco (clock to output) constraint was put in place in the design for an 8 bit register to the 8 bit wide data bus. The 8 bit signal must pass through a bit of combinational logic before arriving at the output.
    Anyway the Tco constraint was inserted with a value of 10ns, but in Quartus the classic timing analyzer informs me that it can´t be done and that the time is 11 ns for each of the bits.

    Now when doing the timing simulation and looking at the signals, I see a delay of 14 ns. Does anyone know why there could be a descrepancy of 3 ns between what Quartus says and what modelsim produces? (I don´t think its clock skew as I am lookinga t the clok signal in the register of the signal)

    I´m assuming that both Quartus and Modelsim are using the worst case (slowest) model. I was expecting that both times would have been quite close. Please let me know if anyone has any ideas?

    Thanks
    Ardni, Oct 28, 2008
    #1
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