Timing results without synthesis?

Discussion in 'VHDL' started by Sergey Katsev, Oct 14, 2006.

  1. Hi all,

    As can be seen by my "VHDL Fixed Point Package" thread problems, I'm
    having some synthesis problems with that package.

    It appears as though the code *is* synthesizeable, just not by ISE,
    right now.

    That being said, are there any existing methodologies to get even
    approximate timing results (both number of clock cycles and
    propagations) for my design without synthesizing it? The design is
    basically a couple of inter-connected systolic arrays which do
    intermediate mathematical operations...

    Thanks,

    Sergey
     
    Sergey Katsev, Oct 14, 2006
    #1
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  2. Sergey Katsev

    radarman Guest

    Sergey Katsev wrote:
    > Hi all,
    >
    > As can be seen by my "VHDL Fixed Point Package" thread problems, I'm
    > having some synthesis problems with that package.
    >
    > It appears as though the code *is* synthesizeable, just not by ISE,
    > right now.
    >
    > That being said, are there any existing methodologies to get even
    > approximate timing results (both number of clock cycles and
    > propagations) for my design without synthesizing it? The design is
    > basically a couple of inter-connected systolic arrays which do
    > intermediate mathematical operations...
    >
    > Thanks,
    >
    > Sergey


    Actual timing will depend on the part, speed grade, routing, and amount
    of combinational logic between registers among other things. Most of
    those factors are component specific. So, while you could estimate
    based on timing figures in the data sheet, they really won't be all
    that useful.

    A better use of time would probably be determining why ISE can't
    compile your code. I haven't seen very much "clean" code fail to
    compile properly under ISE (though I have seen some - so it's not out
    of the question). Also, if you have access to Modelsim, run your code
    through it with the "check for synthesis" option turned on. You might
    be surprised at what it flags.
     
    radarman, Oct 15, 2006
    #2
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  3. Sergey Katsev wrote:

    > As can be seen by my "VHDL Fixed Point Package" thread problems, I'm
    > having some synthesis problems with that package.
    >
    > It appears as though the code *is* synthesizeable, just not by ISE,
    > right now.


    Get the free version on altera quartus, and try it there.
    Quartus is very compliant ieee standards and might work for you.

    -- Mike Treseler
     
    Mike Treseler, Oct 15, 2006
    #3
  4. radarman wrote:

    > A better use of time would probably be determining why ISE can't
    > compile your code. I haven't seen very much "clean" code fail to
    > compile properly under ISE (though I have seen some - so it's not out
    > of the question).


    Other posters have noted that one problem is
    negative array indexes. Legal VHDL but not supported yet by ISE

    > Also, if you have access to Modelsim, run your code
    > through it with the "check for synthesis" option turned on. You might
    > be surprised at what it flags.


    All I've ever found is sensitivity list warnings
    that make no sense for synchronous processes.

    -- Mike Treseler
     
    Mike Treseler, Oct 15, 2006
    #4
  5. Sergey Katsev

    DualCore

    Joined:
    Sep 27, 2006
    Messages:
    4
    synthesis

    well you can port vhd files generated by ise into modelsim , creating new libraries i.e "simprim" , unisim . etc and then compile it .
     
    DualCore, Oct 17, 2006
    #5
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