Timing Simulation - (ModelSim)

Discussion in 'VHDL' started by Abs, Aug 21, 2006.

  1. Abs

    Abs Guest

    HI.

    Well this FAQ has been very kind to me and wish it to be the same for
    all learners.
    What my main prob is, i want to learn "TIMING SIMULATION". I'am
    basically a Front end Verification engineer, i have no idea on Timing
    Simulation. SUppose i have a simple design in VHDL. say a counter. i
    have done the functionality simulation and now want to try out the
    timing simualtion. i was told timing sim. is only for designers and not
    for verification engineers. But i want to get some idea may never know
    when it will be help full.

    I just tried out the timing simulation run and i found out that i need
    to add few libraries and few files. (guess the library files are for
    ModelSim) i have no idea what i'am supposed to do or what files and
    libraries i need to add in order to get the simulation. I'am using
    Xilinx editor and ModelSim Simulation tool. could anyone out here plz
    tell me, how to generate a file from modelsim after functionality
    simulation and what kind of files to add.it will be really helpfull.

    Thanks and lots.
    CHEERS!!
     
    Abs, Aug 21, 2006
    #1
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  2. Abs

    Hubble Guest

    Abs schrieb:

    > Suppose i have a simple design in VHDL. say a counter. i
    > have done the functionality simulation and now want to try out the
    > timing simualtion. i was told timing sim. is only for designers and not
    > for verification engineers. But i want to get some idea may never know
    > when it will be help full.


    You will need a timing model of your design. This is usually done by a
    synthesis tool
    like Synopsys Design Compiler or Leonardo Spectrum and a Layout Tool.

    1. Synthesis.
    ==========
    The synthesis tools create a netlist with some asumptions on timing.
    The netlist
    can be a VHDL (or Verilog) netlist. Then, a SDF file provides the
    timing, usually for
    min, max and typ. (SDF stands for Standard delay format)

    Max timing gives the overall max frequency. If you exceed the max
    frequency,
    the setup time at the longest (logic) path in the design is violated.
    But min timing is also important, since many components like ffs have
    hold times.
    Say, a DFF needs >10 ps before the clock to deliver a stable output at
    Q.

    The clock is also not exaclty delivered to all components, which is an
    issue
    if the logic beween two stages is faster than the uncertainty of the
    clock
    (say: clock tree).

    2. Layout
    =======
    The layout tool leaves the netlist (mostly) alone, but provides
    another,
    now correct, SDF file containing all min/max/typ times for all paths.

    3. Analysis of the timing
    ==================
    Timing analysis can be done
    a) statically by a static timing analysis (which uses algorithms to
    discover hold/setup
    violations/longest paths a.s.o.)

    b) by simulation
    You have a model (your counter) and a testbench
    You have a netlist with a VHDL and SDF file

    Then:
    Keep the testbench, but replace the model with the VHDL netlist.

    The testbench with the VHDL-netlist and the SDF-File can be loaded
    into,
    say, the modelsim simulator doing a simulation. The netlist
    replaces your design
    with the output of the synthesis/layout.

    On simulation of the netlist (which is timing simulation), all
    tests must (should) pass.
    The simulation must not (shoud not) output timing violations (setup
    or hold
    violations).

    Simulate min/max conditions separately (selectable in the
    simulator).
    If you select max SDF Timings, the simulation will represent the
    correct timing under
    low voltage/high temperator (e.g. 3.0V, 85°C).

    If you select min SDF timings, the simulation will represent the
    correct timing under
    high voltage/low temperator (e.g. 3.6V, -25°C).

    4. What is it for
    ===========
    The static timing analysis is absolutely required, since simulation
    cannot simulate
    *all* paths in compex designs. (Example 32x32 bit multiplier needs
    2**64 inputs
    to do a full simulation - impossible).

    Timing simulation gives a confidence on the correctness of the
    synthesis/layout.

    5. Further comments
    ===============
    The designs should be synchroneous with few (only one) clocks (say
    clock domains).
    Then:
    * The setup/hold timings can be detected automatically for internal
    designs
    * Internal timing is mostly verified by static timing analysis.
    * you must specify timing requirements for inputs/outputs and clock
    domain crossings.
    * The timings at the I/O pins and crossings can be verified by
    timing simulation

    Detection of setup/hold time violations is much more precise if you use
    only
    master/slave flip flops (say: registers) an NO (!) latches, which also
    reduces spikes.

    Hubble.
     
    Hubble, Aug 22, 2006
    #2
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  3. Abs

    Abs Guest

    Hey Hubble..
    thanks a lot....
    will implement this idea. very usefull note though. thanks a lot.

    cheers Abs
     
    Abs, Aug 22, 2006
    #3
  4. Abs

    backhus Guest

    Abs schrieb:
    > Hey Hubble..
    > thanks a lot....
    > will implement this idea. very usefull note though. thanks a lot.
    >
    > cheers Abs
    >

    Hi Abs,
    very good posting from Hubble.
    Maybe you already have discovered that the Xilinx Tools (ISE) create you
    all the necessary files (Netlist, SDF) for timing simulation. It can be
    found in the PAR section of the implementation tools.

    have a nice simulation
    Eilert
     
    backhus, Aug 23, 2006
    #4
  5. Abs

    Abs Guest

    HI,

    thanks for all your support, i landed up in some kind of warning. Cant
    really figure out what it is, what it basically tries to signify.

    the warning is:
    ----------------------------------------------------------------------------------------------------------------
    Started process "Generate Post-Map Simulation Model".

    WARNING:Anno:28 - This .ncd is not completely routed; therefore, some
    delay
    calculations may be inaccurate.
    Completed process "Generate Post-Map Simulation Model".
    ----------------------------------------------------------------------------------------------------------------

    I then loaded the netlist and the SDF file and tried to do the timing
    simulation and i got this warning in my modelSim Simulator.
    ----------------------------------------------------------------------------------------------------------------
    # Reading C:/Modeltech_xe/tcl/vsim/pref.tcl
    # do fibo_tb_fibo_vhd_tb.tdo
    # ** Warning: (vlib-34) Library already exists at "work".
    # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26
    2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # ** Error: (vcom-19) Failed to access library 'simprim' at
    "C:\Modeltech_xe\win32xoem/../xilinx/vhdl/simprim".
    # No such file or directory. (errno = ENOENT)
    # ** Error: fibo_timesim.vhd(18): Library simprim not found.
    # ** Error: fibo_timesim.vhd(19): Unknown identifier 'simprim'.
    # ** Error: fibo_timesim.vhd(20): Unknown identifier 'simprim'.
    # ** Error: fibo_timesim.vhd(22): VHDL Compiler exiting
    # ** Error: C:/Modeltech_xe/win32xoem/vcom failed.
    # Error in macro ./fibo_tb_fibo_vhd_tb.tdo line 6
    # C:/Modeltech_xe/win32xoem/vcom failed.
    # while executing
    # "vcom -87 -explicit fibo_timesim.vhd
    # "
    ----------------------------------------------------------------------------------------------------------------

    Could i get info and help regarding what this is, and how am i suposed
    to carry on with the timing simulation.

    Thanks and regards...
     
    Abs, Aug 25, 2006
    #5
  6. Abs

    Hubble Guest

    Abs schrieb:


    > the warning is:
    > ----------------------------------------------------------------------------------------------------------------
    > Started process "Generate Post-Map Simulation Model".
    >
    > WARNING:Anno:28 - This .ncd is not completely routed; therefore, some
    > delay
    > calculations may be inaccurate.
    > Completed process "Generate Post-Map Simulation Model".
    > ----------------------------------------------------------------------------------------------------------------
    >
    > I then loaded the netlist and the SDF file and tried to do the timing
    > simulation and i got this warning in my modelSim Simulator.
    > ----------------------------------------------------------------------------------------------------------------
    > # Reading C:/Modeltech_xe/tcl/vsim/pref.tcl
    > # do fibo_tb_fibo_vhd_tb.tdo
    > # ** Warning: (vlib-34) Library already exists at "work".
    > # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26
    > 2004
    > # -- Loading package standard
    > # -- Loading package std_logic_1164
    > # ** Error: (vcom-19) Failed to access library 'simprim' at
    > "C:\Modeltech_xe\win32xoem/../xilinx/vhdl/simprim".
    > # No such file or directory. (errno = ENOENT)
    > # ** Error: fibo_timesim.vhd(18): Library simprim not found.
    > # ** Error: fibo_timesim.vhd(19): Unknown identifier 'simprim'.
    > # ** Error: fibo_timesim.vhd(20): Unknown identifier 'simprim'.
    > # ** Error: fibo_timesim.vhd(22): VHDL Compiler exiting
    > # ** Error: C:/Modeltech_xe/win32xoem/vcom failed.
    > # Error in macro ./fibo_tb_fibo_vhd_tb.tdo line 6
    > # C:/Modeltech_xe/win32xoem/vcom failed.
    > # while executing
    > # "vcom -87 -explicit fibo_timesim.vhd
    > # "
    > ----------------------------------------------------------------------------------------------------------------
    >
    > Could i get info and help regarding what this is, and how am i suposed
    > to carry on with the timing simulation.
    >


    You need to install the (Xilinx) SIMPRIM libraries. Probably

    http://www.sital.co.il/pdf/Xilinx_VHD_gtl.pdf

    shoud help you

    Hubble
     
    Hubble, Aug 25, 2006
    #6
  7. Abs

    Abs Guest

    Hi Hubble
    thanks for your speedy reply..
    well, i wana know, how d i tackle with this issue.

    > > the warning is:
    > > ----------------------------------------------------------------------------------------------------------------
    > > Started process "Generate Post-Map Simulation Model".
    > >
    > > WARNING:Anno:28 - This .ncd is not completely routed; therefore, some
    > > delay
    > > calculations may be inaccurate.
    > > Completed process "Generate Post-Map Simulation Model".
    > > ----------------------------------------------------------------------------------------------------------------



    for my former prob. all i need to do is, is install the required
    labrary, SPRIM.

    Thanks.
    Cheers
     
    Abs, Aug 25, 2006
    #7
  8. Abs

    Hubble Guest

    Abs schrieb:

    ----------------------------------------------------------------------------------------------------------------
    > > > Started process "Generate Post-Map Simulation Model".
    > > >
    > > > WARNING:Anno:28 - This .ncd is not completely routed; therefore, some
    > > > delay
    > > > calculations may be inaccurate.
    > > > Completed process "Generate Post-Map Simulation Model".
    > > > ----------------------------------------------------------------------------------------------------------------

    >
    >
    > for my former prob. all i need to do is, is install the required
    > labrary, SPRIM.


    This seems to be a XILINX problem (I'm not a XILINX expert). I think
    the SDF is imcomplete.
    Maybe have a look at the output of XILINX par tool. Are there any
    syntax errors in your UCF file?

    Hubble.
     
    Hubble, Aug 25, 2006
    #8
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