timing simulation spikes

Discussion in 'VHDL' started by vcc99, Mar 15, 2008.

  1. vcc99

    vcc99

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    nevermind.
    Last edited: Mar 15, 2008
    vcc99, Mar 15, 2008
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  2. vcc99

    jeppe

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    Mar 10, 2008
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    A Dynamic hazard problem

    This spike problem can only arise due to different delays in the "real" circuit.

    You can get rid of this by moving the outval behind the rising_edge(Clk). In other words will it cost you an extra F/F in the design.

    Your dealing with a moore output anyway so this shouldn't give you any delays.

    Best regards
    Jeppe

    Your velcome

    (Glad to see its possible to include code and figures)
    Last edited: Mar 15, 2008
    jeppe, Mar 15, 2008
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