Questio for Kevin:
It was so nice that you went thru those pages and explained them to
me. I followed your statements as I was going thru those pages. Now, I
think I know what I should do (after reviewig these again). My
question for you is "What is the next step? after understanding the
timing/delays ?" let's say I want to control the clock and get the
output expected in those figures using VHDL.
What should I do?
Well first you have to understand functionally how the part works and
what the various input and output signals even do. As a rough guide,
every input to the device you're trying to control (i.e. the 'Wolson
WM8731 CODEC and FIFO') will come from an output on your FPGA.
Similarly, every output of your device will most likely connect to an
input to your FPGA. How the FPGA would connect to anything else in
your system, I haven't a clue since all you said earlier is "I have
given a project to read some
music files..." so presumably you already know how you're getting
those music files into whatever device it is (the FPGA?) that then
connects to the CODEC, but maybe your design isn't worked out even
that much. In any case, you're likely trying to move bytes of data
from somewhere into the CODEC so you'll need to understand what format
the CODEC wants those bytes of data and how you need to control the
CODEC in order to accomplish that task.
1. Study the entire data sheet, not just the timing diagrams.
2. Come up with a VHDL design for the FPGA that will control the
CODEC.
3. Come up with a VHDL model for the CODEC. Maybe you can get it from
the supplier, maybe you'll have to write it yourself based on your
understanding of the part that was gleaned from step #1. If you don't
have the understanding to write such a model yourself, then you also
most likely don't have the understanding to successfully complete step
#2.
4. Create a testbench that connects the FPGA to the CODEC (and
whatever it is that will get the music files into the FPGA in the
first place) and simulate the system. Once you can simulate correctly
and move data from the 'music files' all the way through the system
into the CODEC, then you're probably ready to try it out on a real
board. Until that time, you're better off debugging in simulation
(it's much faster to find/fix errors).
Is there any samples? do I need to create an Entity with the same
input/output ports and try to get an output exactly to those figures
on page 15?
You're trying to get things to meet requirements not match some
figure. For example, if some signal has a 10ns minimum setup time
requirement, then that does not mean you need to get the signal there
precisely 10ns before, anything larger than 10ns would do.
Things to consider that cause heartahces are signals that have both
setup time and non-zero hold time requirements (I think your CODEC had
those). One usually relatively easy to meet such requirements if the
clock isn't running too fast is to send those signals on the opposite
edge of the clock that the device is looking for them. That way
you're guaranteed that the signals are stable both before and after
the point where the device needs them since they will be there
nominally 1/2 clock cycle both before and after the sampling edge.
If you're asking for a completed design to do all of this though, you
likely won't find it by posting questions in a newsgroup without a
contract to pay for such design services.
Kevin Jennings