Tips for handling switch bounce?

Discussion in 'VHDL' started by Hillam, May 8, 2012.

  1. Hillam

    Hillam

    Joined:
    May 8, 2012
    Messages:
    1
    Hi everyone,

    I was just wondering if anyone had any suggestions on how to accommodate for bounce on push button switches on an FPGA board. The boards are quite old (10+ years) and apparently the switches have reached the "pretty dodgy" stage (to quote the lecturer). I'm trying to implement some logic I came up with for a state machine that deals with a combination lock; pressing a series of buttons in the correct sequence unlocks a door, making a mistake sends it to an "alarm" state which remains in place until the reset switch is pushed. Problem is that the switches are so "pretty dodgy" that pushing the first button sends it straight to the alarm state (either that or my code implementation sucks; not dismissing that as an option either). I've tried using wait statements so far, but no success. Any ideas?
    Hillam, May 8, 2012
    #1
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  2. Hillam

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Hi

    Instead of depending on a single value from a "poor switch" must you collect several values. Could be done in a shiftregister with say 8 bits.

    Shreg <= Shreg( 6 downto 0) & Switch;

    00000000 => Steady 0
    01101011 => Push down with bounces
    01111111 => Accepted "rising edge"
    11111111 => Steady 1
    10110110 => Release with bounces
    10000000 => Accepted "falling edge"

    The best frequency for the detection could be around 1 kHz and the length of the shiftregister could be longer/shorter as well.

    Your welcome
    Last edited: May 9, 2012
    jeppe, May 9, 2012
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  3. Hillam

    nitram

    Joined:
    May 17, 2012
    Messages:
    1
    simple module which take care about metastability and debounce

    Hi,

    I'm using simple module which take care about metastability and debounce.

    HTML:
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.numeric_std.ALL;
    
    ENTITY debounce IS
      GENERIC (
        width : NATURAL;
        active_level : STD_LOGIC
      );
      PORT (
        clk : IN STD_LOGIC;
        async_in : IN STD_LOGIC;
        sync_out : OUT STD_LOGIC
      );
    END;
    
    ARCHITECTURE rtl OF debounce IS
      SIGNAL dff1_q : STD_LOGIC := not active_level;
      SIGNAL dff2_q : STD_LOGIC := not active_level;
      SIGNAL cnt : UNSIGNED(width - 1 DOWNTO 0) := (OTHERS => '1');
    BEGIN
      -- metastability remover
      PROCESS (clk)
      BEGIN
        IF rising_edge(clk) THEN
          dff1_q <= async_in;  -- first DFF
          dff2_q <= dff1_q;    -- second DFF
        END IF;
      END PROCESS;
    
      -- debouncer
      PROCESS (clk, dff2_q)
      BEGIN
        -- asynchronous reset
        IF dff2_q = active_level THEN
          cnt <= (OTHERS => '0');
          sync_out <= active_level;
        -- debounce counter
        ELSIF rising_edge(clk) THEN
          IF cnt = (2**width - 1) THEN
            sync_out <= NOT active_level;
          ELSE
            cnt <= cnt + 1;
          END IF;
        END IF;
      END PROCESS;
    END;
    
    Martin
    nitram, May 17, 2012
    #3
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