To generate a periodic time-gate

Discussion in 'VHDL' started by vizziee@gmail.com, Nov 21, 2005.

  1. Guest

    Hello,

    I want to generate a signal which is periodically toggling for a
    specified time of the order of, say 2 seconds i.e. it is like a clock
    with 4 sec period.

    What is available to me is a clock of 4MHz frequency.

    I used the following approach, rather unsuccessfully: I used a counter
    (a 20-bit counter rather ) to count the clock periods till it amounted
    to 2 seconds. Using counter values I am toggling my output signal in a
    concurrent statement. The counter should reset after 4 seconds but
    since this counter doesn't count all the 20-bit values, it doesn't
    reset automatically after 4 sec. So what can be the workaround? Can I
    avoid a counter with 20-bits and do with a smaller one?

    Sincerely,
     
    , Nov 21, 2005
    #1
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  2. jens Guest

    It sounds like you need a 23-bit counter... when 2s expires toggle your
    output signal and reset the counter so it can count 2s again.

    An LFSR is a small and fast counter that would be well-suited for this
    application.

    However, if you're using this for an internal signal, you're better off
    using an enable signal instead of another clock signal (i.e. keep the
    design synchronous).
     
    jens, Nov 21, 2005
    #2
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  3. OutputLogic

    Joined:
    May 20, 2009
    Messages:
    8
    Online LFSR counter generator

    There is an online tool that generates a Verilog code for LFSR Counters of any value up to 31-bit wide. It's on "http OutputLogic dot com" [sorry, this site doesn't let me post a link in a regular way]
    LFSR counters are much smaller than regular ones. Looks like that's what you need.
     
    OutputLogic, May 22, 2009
    #3
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