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Discussion in 'VHDL' started by chaitanyakurmala@gmail.com, Sep 13, 2006.

  1. Guest

    dear ram add source or add new source
    let me say i right click device and add new source and in that i
    selected VHDL package.and defined the package and saved. again right
    click the device and add new source and selected vhdlmodule and written
    my design ( in this i called that package defined previously as use
    work.adderpackage.all)will it show any error at any point of design
    flow. and one more thing do i have to verify the functionality of
    package or just syntax checking is enough)
    , Sep 13, 2006
    #1
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