to_stdlogicvector and to_unsigned

[seinal]

HI all,

I'm new to the newsgroup.

I'm starting with VHDL and I'm working with ISE Foundation 8.2i.

Implementing the following code from the "Essential VHDL" book, from Sundar Rajan, I've got 2 errors that I don't know how to solve:
/////////////////////////////////////////////////////////
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;

architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0):="0000";
begin

process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;

q <= to_stdlogicvector(qLocal);

end rtl;
//////////////////////////////////////////////////////
Compiling vhdl file "D:/11-VHDL/Proyectos/Cap7/ldcnta.vhd" in Library work.
ERROR:HDLParsers:3324 - "D:/11-VHDL/Proyectos/Cap7/ldcnta.vhd" Line 22. IN mode Formal SIZE of to_unsigned with no default value must be associated with an actual value.
ERROR:HDLParsers:808 - "D:/11-VHDL/Proyectos/Cap7/ldcnta.vhd" Line 28. to_stdlogicvector can not have such operands in this context.
///////////////////////////////////////////////////////
I've tried writing the size of qLocal and q (3 downto 0) but it hasn't worked.

Any help would be appreciated. Thanks in advance!

 

[jeppe]

q <= conv_std_logic_vector(qLocal,4); -- Try this

Jeppe

 

[seinal]

library/function issue

Hi,

Problem resolved. Thank you Jeppe!

Using the conv_std_logic_vector(qlocal,4) with the library
ieee.std_logic_arith.all
To solve the problem with "to_unsigned" function, looking at its definition in the "ieee.numeric_std" library, it is defined as a conversion from INTEGER to UNSIGNED, not from STD_LOGIC_VECTOR (SLV).

So to solve that conversion I've used 2 functions:

qLocal <= conv_unsigned(conv_integer(loadVal),4);--to_unsigned(loadVal)

I have had to add the library "ieee.std_logic_unsigned.all" in order to use conv_unsigned function.

If someone knows a way for converting in 1 step from SLV to unsigned, please advise.

Thanks

 

[jeppe]

Glad to learn your problem solved.
It will be ok to use two conversion function - it won't cost you extra hardware as the function mostly because of the strong type-dependiency of VHDL.

Jeppe