to_stdlogicvector ERROR

Discussion in 'VHDL' started by sebs, Nov 11, 2008.

  1. sebs

    sebs Guest

    Hey,

    I have a unsigned to std_logic_vector conversion and I get the
    following error:

    "to_stdLogicVector can not have such operands in this context."

    I'm using Xilinx EDK 8.1

    Here is some of my code to explain where the errror occurs.

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    M_ABus : out std_logic_vector(0 to 31);


    signal row_cnt : unsigned(0 to 9);
    signal row_cnt_en : std_logic;
    signal row_rst : std_logic;


    addr_counter : process(PLB_Clk, PLB_Rst)
    begin
    if PLB_Clk'event and PLB_Clk = '1' then
    if row_cnt_en = '1' then
    row_cnt <= row_cnt + 1;
    end if;
    end if;
    if (PLB_RST or row_rst) = '1' then
    row_cnt <= (others => '0'); -- 768-1
    end if;
    end process;

    M_ABus(11 to 20) <= to_stdLogicVector(row_cnt); -- the error
    occurs in this line.

    Hope someone can help me with this.

    Sebastian
     
    sebs, Nov 11, 2008
    #1
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  2. sebs

    Guest

    On Nov 11, 7:11 am, sebs <> wrote:
    > Hey,
    >
    > I have a unsigned to std_logic_vector conversion and I get the
    > following error:
    >
    > "to_stdLogicVector can not have such operands in this context."
    >
    > I'm using Xilinx EDK 8.1
    >
    > Here is some of my code to explain where the errror occurs.
    >
    > library ieee;
    > use ieee.std_logic_1164.all;
    > use ieee.numeric_std.all;
    >
    >   M_ABus     : out std_logic_vector(0 to 31);
    >
    >  signal row_cnt      : unsigned(0 to 9);
    >  signal row_cnt_en   : std_logic;
    >  signal row_rst      : std_logic;
    >
    > addr_counter : process(PLB_Clk, PLB_Rst)
    >  begin
    >    if PLB_Clk'event and PLB_Clk = '1' then
    >      if row_cnt_en = '1' then
    >        row_cnt <= row_cnt + 1;
    >      end if;
    >    end if;
    >    if (PLB_RST or row_rst) = '1' then
    >      row_cnt <= (others => '0');   -- 768-1
    >    end if;
    >  end process;
    >
    >   M_ABus(11 to 20) <= to_stdLogicVector(row_cnt);   -- the error
    > occurs in this line.
    >
    > Hope someone can help me with this.
    >
    > Sebastian


    The function To_StdLogicVector() is defined for BIT_VECTOR, and
    STD_ULOGIC_VECTOR only. But you're passing it an UNSIGNED. Even
    though STD_UNLOGIC_VECTOR smells kind of like an UNSIGNED, it's a
    different type. However, the element types of std_logic_vector and
    unsigned are both std_logic though, so you could just pass them
    element by element:

    for i in 11 to 20 generate
    m_ABus(i) <= row_cnt(i-11);
    end generate;

    I might be missing some obvious library conversion function, on the
    other hand :-(

    - Kenn
     
    , Nov 11, 2008
    #2
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  3. sebs

    KJ Guest

    On Nov 11, 7:11 am, sebs <> wrote:

    > Hope someone can help me with this.


    M_ABus(11 to 20) <= std_logic_vector(row_cnt);

    KJ
     
    KJ, Nov 11, 2008
    #3
  4. sebs

    sebs Guest

    On 11 Nov., 13:58, KJ <> wrote:
    > On Nov 11, 7:11 am, sebs <> wrote:
    >
    > > Hope someone can help me with this.

    >
    > M_ABus(11 to 20) <= std_logic_vector(row_cnt);
    >
    > KJ


    Thanks KJ that works

    @Kenn

    To_stdlogicvector is defined in ieee.numeric_std.all as

    function TO_STDLOGICVECTOR ( ARG: UNSIGNED) return STD_LOGIC_VECTOR;
    -- Result subtype: STD_LOGIC_VECTOR, same range as input ARG
    -- Result: Converts UNSIGNED to STD_LOGIC_VECTOR.
     
    sebs, Nov 11, 2008
    #4
  5. sebs

    KJ Guest

    On Nov 11, 8:02 am, sebs <> wrote:

    > To_stdlogicvector is defined in ieee.numeric_std.all  as
    >
    >  function TO_STDLOGICVECTOR ( ARG: UNSIGNED) return STD_LOGIC_VECTOR;
    >      -- Result subtype: STD_LOGIC_VECTOR, same range as input ARG
    >      -- Result: Converts UNSIGNED to STD_LOGIC_VECTOR.


    You might want to check your source that you got numeric_std from.
    The to_stdlogicvector type conversion function was removed from the
    final version of the IEEE standard in 1993.

    KJ
     
    KJ, Nov 11, 2008
    #5
  6. sebs

    Guest

    On Nov 11, 8:02 am, sebs <> wrote:
    >
    > @Kenn
    >
    > To_stdlogicvector is defined in ieee.numeric_std.all  as
    >
    >  function TO_STDLOGICVECTOR ( ARG: UNSIGNED) return STD_LOGIC_VECTOR;
    >      -- Result subtype: STD_LOGIC_VECTOR, same range as input ARG
    >      -- Result: Converts UNSIGNED to STD_LOGIC_VECTOR.


    OK, I'll embarrass myself publicly and ask where (in what version,
    from what web documentation, etc) that's defined. I was admittedly
    looking at a very old numeric_std, but I still don't see it in the
    200x packages at vhdl.org nor in my (admittedly old) tool copies.

    And what am I missing here? If that function really is defined and is
    visible as stated, then why doesn't the OP's code work?

    I'm feeling like I'm starting to imagine things here...

    - Kenn
     
    , Nov 11, 2008
    #6
  7. sebs

    loris

    Joined:
    Jul 18, 2008
    Messages:
    3
    Sorry, but is not defined the function TO_STDLOGICVECTOR in the Std_Logic_1164 package? :stupido:
     
    loris, Nov 27, 2008
    #7
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