transaction recording

Discussion in 'VHDL' started by John Smith, Oct 18, 2009.

  1. John Smith

    John Smith Guest

    Hi,

    Is there any way to record and write transactions to a textfile in
    modelsim? I found that is possible for verilog and for systemc but
    nothing found for vhdl.

    Thanks
    John Smith, Oct 18, 2009
    #1
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  2. John Smith wrote:

    > Hi,
    >
    > Is there any way to record and write transactions to a textfile in
    > modelsim? I found that is possible for verilog and for systemc but
    > nothing found for vhdl.


    What exactly do you mean with transactions?

    In ModelSim there is the list window that shows all events on a signal with
    the capability to save the results as a textfile in various forms. I'm not
    sure if this is what you mean.

    And of course there are the standard writeline and report statements to
    produce output in a textfile.

    --
    Paul Uiterlinden
    www.aimvalley.nl
    e-mail addres: remove the not.
    Paul Uiterlinden, Oct 20, 2009
    #2
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  3. John Smith

    JohnSmith Guest

    On Oct 20, 5:36 pm, Paul Uiterlinden <> wrote:
    > John Smith wrote:
    > > Hi,

    >
    > > Is there any way to record and write transactions to a textfile in
    > > modelsim? I found that is possible for verilog and for systemc but
    > > nothing found for vhdl.

    >
    > What exactly do you mean with transactions?
    >
    > In ModelSim there is the list window that shows all events on a signal with
    > the capability to save the results as a textfile in various forms. I'm not
    > sure if this is what you mean.
    >
    > And of course there are the standard writeline and report statements to
    > produce output in a textfile.
    >
    > --
    > Paul Uiterlindenwww.aimvalley.nl
    > e-mail addres: remove the not.


    When I run my design, there is an unexpected value in a signal. I
    would like to know who (which statement) is the responsible for that.

    Thanks
    JohnSmith, Oct 20, 2009
    #3
  4. JohnSmith wrote:

    > When I run my design, there is an unexpected value in a signal. I
    > would like to know who (which statement) is the responsible for that.


    I would trace code and set breakpoints.

    -- Mike Treseler
    Mike Treseler, Oct 20, 2009
    #4
  5. John Smith

    KJ Guest

    On Oct 20, 4:54 pm, JohnSmith <> wrote:

    >
    > When I run my design, there is an unexpected value in a signal. I
    > would like to know who (which statement) is the responsible for that.
    >


    Well, that's an easy question to answer. Your design, you're
    responsible.

    If by 'unexpected' you mean an 'X' or 'U' or something like
    that...then use the 'drivers' command. It lists all of the drivers of
    a net, helps you find 'unexpected' cases of multiple drivers. Then
    try using type 'std_ulogic' rather than 'std_logic' as your basic type
    and you won't have to debug to find such errors ever again; the
    compiler will flag multiple drivers as an error. Use std_logic only
    for the few cases where it really is permissible to have multiple
    drivers.

    If by 'unexpected' you mean you got 'ABCD' on some data bus rather
    than '1234' than you'll have to debug that yourself. Modelsim has all
    of the debug utilities (wave, list, source code, dataflow windows,
    breakpoints, etc.). Log all of the signals in your design at the
    start of sim (command "log -r /*") and you'll have the complete
    history of every change that ever occurs on every signal. Can't get
    more complete than that.

    KJ
    KJ, Oct 21, 2009
    #5
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