transaction vs event

Discussion in 'VHDL' started by canadianJaouk, Nov 3, 2006.

  1. Does anyone know what the difference between <signal>'event and
    <signal>'transaction is? Anyone has a precise definition of these
    keywords?

    Thanks
    -Jake
    canadianJaouk, Nov 3, 2006
    #1
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  2. On 3 Nov 2006 11:31:10 -0800, "canadianJaouk"
    <> wrote:

    >Does anyone know what the difference between <signal>'event and
    ><signal>'transaction is? Anyone has a precise definition of these


    <sig>'event is a boolean value that is TRUE in a delta cycle when
    <sig> has just changed, and FALSE at other times. You can test
    'event in an IF statement. Take, for example, the not-very-pretty
    traditional form of clocked process:

    process(clk, rst)
    begin
    if rst='1' then
    -- do reset actions
    elsif clk='1' and clk'event then
    -- clk has just changed to '1', and
    -- that change triggered the process
    -- so do clocked actions

    <sig>'transaction allows you to check whether some assignment was
    made to the signal, even if that assignment didn't change the
    signal's value. <sig>'transaction is a completely new signal,
    of type BIT, that toggles from '0' to '1' or back again in each
    delta cycle when one or more assignment is made to <sig>.
    This is occasionally useful if you have a data structure representing
    a transaction, and you would like to detect when someone puts
    a new value on that data structure - even if it's the same as
    the existing value. Because it's a new signal in its own right,
    you can use it in a sensitivity list...

    wait on thing'transaction;
    -- someone has written to "thing"
    -- so we need to process the new value

    Fairly obviously, 'transaction is not synthesisable. 'event is
    synthesisable in a few special cases.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Nov 3, 2006
    #2
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  3. Thanks very much. That's exactly what i was looking for. I have
    further questions however.

    I have seen the 'transaction used in a statement that looks like this:

    wait on <sig>'transaction until <some condition>

    what does the until <some condition> means in this context?

    On Nov 3, 4:54 pm, Jonathan Bromley <>
    wrote:
    > On 3 Nov 2006 11:31:10 -0800, "canadianJaouk"
    >
    > <> wrote:
    > >Does anyone know what the difference between <signal>'eventand
    > ><signal>'transactionis? Anyone has a precise definition of these<sig>'eventis a boolean value that is TRUE in a delta cycle when

    > <sig> has just changed, and FALSE at other times. You can test
    > 'eventin an IF statement. Take, for example, the not-very-pretty
    > traditional form of clocked process:
    >
    > process(clk, rst)
    > begin
    > if rst='1' then
    > -- do reset actions
    > elsif clk='1' and clk'eventthen
    > -- clk has just changed to '1', and
    > -- that change triggered the process
    > -- so do clocked actions
    >
    > <sig>'transactionallows you to check whether some assignment was
    > made to the signal, even if that assignment didn't change the
    > signal's value. <sig>'transactionis a completely new signal,
    > of type BIT, that toggles from '0' to '1' or back again in each
    > delta cycle when one or more assignment is made to <sig>.
    > This is occasionally useful if you have a data structure representing
    > atransaction, and you would like to detect when someone puts
    > a new value on that data structure - even if it's the same as
    > the existing value. Because it's a new signal in its own right,
    > you can use it in a sensitivity list...
    >
    > wait on thing'transaction;
    > -- someone has written to "thing"
    > -- so we need to process the new value
    >
    > Fairly obviously, 'transactionis not synthesisable. 'eventis
    > synthesisable in a few special cases.
    > --
    > Jonathan Bromley, Consultant
    >
    > DOULOS - Developing Design Know-how
    > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
    >
    > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
    > ://www.MYCOMPANY.com
    >
    > The contents of this message may contain personal views which
    > are not the views of Doulos Ltd., unless specifically stated.
    canadianJaouk, Nov 16, 2006
    #3
  4. canadianJaouk

    Jim Lewis Guest

    canadianJaouk wrote:
    > I have seen the 'transaction used in a statement that looks like this:
    >
    > wait on <sig>'transaction until <some condition>
    >
    > what does the until <some condition> means in this context?


    Whenever the signal "<sig>'transaction" changes, "<some condition>"
    is evaluated and when "<some condition>" is true, the
    wait statement wakes up.


    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis, Nov 16, 2006
    #4
  5. Here is a transcript of the evolution of a signal through time. The
    value clearly changes, but the signal's transaction signal is always ?
    Should it not go to 1 as soon as the signal value changes? Any ideas?

    time delta value value'transaction
    0 +0 -1e+308 ?
    0 +2 -1e+100 ?
    0 +3 400 ?
    10 +4 -1e+100 ?
    10 +5 2.4 ?

    On Nov 15, 9:17 pm, Jim Lewis <> wrote:
    > canadianJaouk wrote:
    > > I have seen the 'transactionused in a statement that looks like this:

    >
    > > wait on <sig>'transactionuntil <some condition>

    >
    > > what does the until <some condition> means in this context?Whenever the signal "<sig>'transaction" changes, "<some condition>"

    > is evaluated and when "<some condition>" is true, the
    > wait statement wakes up.
    >
    > --
    > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    > Jim Lewis
    > Director of Training mailto:
    > SynthWorks Design Inc. http://www.SynthWorks.com
    > 1-503-590-4787
    >
    > ExpertVHDLTraining for Hardware Design and Verification
    > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    canadianJaouk, Nov 17, 2006
    #5
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