Transport Triggered Architecture Socket in VHDL

Discussion in 'VHDL' started by lyonscf@gmail.com, Feb 24, 2008.

  1. Guest

    I'm trying to figure out the most efficient way of implementing a TTA
    socket in VHDL.

    I currently have a 24bit control word for each of the function units,
    it looks like this:

    DST sID SRC sID OPCODE
    |----------------------------------------------------|
    | 000000000 | 000000000 | 000000 |
    |----------------------------------------------------|
    | 23 - 15 | 14 - 6 | 5 - 0 |
    |----------------------------------------------------|

    The socket checks the control word coming along each of the 4 control
    buses (as there is 4 data buses) so see if the source or destination
    ID is its own and then lets the data on the appropriate bus and opcode
    into the function unit.

    My current implementation works in two stages, it firstly compares
    each of the control inputs (I0,I1,I2,I3) coming in on the control
    buses with the FUs sID , this will output a select for which bus
    you're taking in from (SO), an enable (EO) and the opcode (OP). The EO
    and SO go into a MUX or DEMUX depending on whether its an input or
    output socket which selects from/to the data bus.

    I have made this too complicated, when synthesizing it comes out for a
    Maximum combinatorial path delay of 7.988ns, which is way too
    expensive, especially when the point of TTA is to be simple and
    therefore fast.

    I'll really appreciate if anyone had any comments, suggestions,
    constructive criticism, maybe I'm even going about this completely
    wrong etc.

    Thanks in advance!

    - Colin
    , Feb 24, 2008
    #1
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  2. HT-Lab Guest

    I believe that TTA/Move is not particular FPGA friendly due to the
    large/many internal busses. Here is my brief attempt to look at this
    fascinating processor architecture, if only I had more time....

    http://www.ht-lab.com/freecores/move/move.html

    Hans
    www.ht-lab.com



    <> wrote in message
    news:...
    >
    > I'm trying to figure out the most efficient way of implementing a TTA
    > socket in VHDL.
    >
    > I currently have a 24bit control word for each of the function units,
    > it looks like this:
    >
    > DST sID SRC sID OPCODE
    > |----------------------------------------------------|
    > | 000000000 | 000000000 | 000000 |
    > |----------------------------------------------------|
    > | 23 - 15 | 14 - 6 | 5 - 0 |
    > |----------------------------------------------------|
    >
    > The socket checks the control word coming along each of the 4 control
    > buses (as there is 4 data buses) so see if the source or destination
    > ID is its own and then lets the data on the appropriate bus and opcode
    > into the function unit.
    >
    > My current implementation works in two stages, it firstly compares
    > each of the control inputs (I0,I1,I2,I3) coming in on the control
    > buses with the FUs sID , this will output a select for which bus
    > you're taking in from (SO), an enable (EO) and the opcode (OP). The EO
    > and SO go into a MUX or DEMUX depending on whether its an input or
    > output socket which selects from/to the data bus.
    >
    > I have made this too complicated, when synthesizing it comes out for a
    > Maximum combinatorial path delay of 7.988ns, which is way too
    > expensive, especially when the point of TTA is to be simple and
    > therefore fast.
    >
    > I'll really appreciate if anyone had any comments, suggestions,
    > constructive criticism, maybe I'm even going about this completely
    > wrong etc.
    >
    > Thanks in advance!
    >
    > - Colin
    HT-Lab, Feb 24, 2008
    #2
    1. Advertising

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