Tristate-Master-Slave testbench description

Discussion in 'VHDL' started by ALuPin@web.de, May 13, 2005.

  1. Guest

    Hi ,
    I want to use the following component instantiation
    in my VHDL testbench:



    entity tb_test is
    end tb_test;

    architecture testbench of tb_test is


    component test
    port ( Reset : in std_logic;
    Clk : in std_logic;
    Bidir_data : inout std_logic_vector(7 downto 0);
    Dir : in std_logic;
    Nxt : in std_logic;
    Stp : out std_logic
    ...
    );
    end component;

    signal t_Reset : std_logic;
    signal t_Clk : std_logic;
    signal t_Bidir_data : std_logic;
    signal t_Dir : std_logic;
    signal t_Nxt : std_logic;
    signal t_Stp : std_logic;
    ....

    signal t_tx_data : std_logic_vector(7 downto 0)
    signal t_drive_tx_data : std_logic;

    signal t_rx_data : std_logic_vector(7 downto 0);


    begin



    uut : test
    port map ( Reset => t_Reset,
    Clk => t_Clk,
    Bidir_data => t_Bidir_data,
    Dir => t_Dir,
    Nxt => t_Nxt,
    Stp => t_Stp
    );

    t_Bidir_data <= t_tx_data when t_drive_tx_data='1' else (others =>
    'Z');
    t_rx_data <= t_Bidir_data when t_drive_tx_data='0' else (others =>
    '0');

    process
    begin
    -- Generate t_tx_data, t_drive_tx_data
    -- in this process
    end process;


    end testbench;



    My question :
    In the port map
    Bidir_data => t_Bidir_data

    an INOUT port of the unit under test is connected to a signal within
    the testbench.

    Will the Tristate Description shown work ? (Which "direction does
    "t_Bidir_data" have ?)
    The testbench "t_tx_data" generation takes over the tristate bus master
    role.


    Thank you for your help

    Rgds
    André
    , May 13, 2005
    #1
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  2. sps Guest

    i guess u won't be able to simulate inout signals....simulator won't
    give error but the signal will be missing
    sps, May 13, 2005
    #2
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  3. Duane Clark Guest

    wrote:
    > ...
    > t_Bidir_data <= t_tx_data when t_drive_tx_data='1' else (others =>
    > 'Z');
    > t_rx_data <= t_Bidir_data when t_drive_tx_data='0' else (others =>
    > '0');
    > ...
    >
    > My question :
    > In the port map
    > Bidir_data => t_Bidir_data
    >
    > an INOUT port of the unit under test is connected to a signal within
    > the testbench.
    >
    > Will the Tristate Description shown work ? (Which "direction does
    > "t_Bidir_data" have ?)
    > The testbench "t_tx_data" generation takes over the tristate bus master
    > role.
    >


    Did you just try it? That would be the easy thing to do. Sure, it will
    work. There is normally no reason to tristate the receive data. Just do

    t_rx_data <= t_Bidir_data;
    Duane Clark, May 13, 2005
    #3
  4. Guest

    sps schrieb:
    > i guess u won't be able to simulate inout signals....simulator won't
    > give error but the signal will be missing


    How can I solve this problem ?
    I must simulate inout signals ... Any alternative ?

    Rgds
    André
    , May 17, 2005
    #4
  5. Neo Guest

    inout simulations work fine in simulator. just simulate your code.
    There is no direction for your "t_Bidir_data". its local to TB.
    Neo, May 17, 2005
    #5
  6. Guest

    Yes, I tried it, and it works.

    Thank you for your help :eek:)

    Rgds
    André
    Duane Clark schrieb:
    > wrote:
    > > ...
    > > t_Bidir_data <= t_tx_data when t_drive_tx_data='1' else (others =>
    > > 'Z');
    > > t_rx_data <= t_Bidir_data when t_drive_tx_data='0' else (others

    =>
    > > '0');
    > > ...
    > >
    > > My question :
    > > In the port map
    > > Bidir_data => t_Bidir_data
    > >
    > > an INOUT port of the unit under test is connected to a signal

    within
    > > the testbench.
    > >
    > > Will the Tristate Description shown work ? (Which "direction does
    > > "t_Bidir_data" have ?)
    > > The testbench "t_tx_data" generation takes over the tristate bus

    master
    > > role.
    > >

    >
    > Did you just try it? That would be the easy thing to do. Sure, it

    will
    > work. There is normally no reason to tristate the receive data. Just

    do
    >
    > t_rx_data <= t_Bidir_data;
    , May 18, 2005
    #6
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