Tristate

[Michael]

hello
I'm having trouble synthesising the following tristate implementation:

-- ...
-- ...
architecture Behavioral of driver is
signal current_state, next_state : std_logic_vector(4 downto 0);
signal tmp : std_logic_vector(1 downto 0);
begin
-- ...
-- ...
out_logic: process(current_state)
begin
case current_state is
when "00001" =>
C_BE <= DEV_RTYP;
FRAME <= '1';
AD <= DEV_ADDR;
IRDY <= 'Z';
when "00010" =>
IRDY <= 'Z';
if LAST = '1' then
FRAME <= '0';
end if;
when others =>
DRV_RDY <= '0';
end case;
end process out_logic;
end Behavioral;

IRDY is a port declared as inout stdlogic. The error I'm getting is :

ERROR:Xst:742 - Unexpected 'Z' expression found.
ERROR:Xst:746 - Failed to build equation for signal <irdy> in unit <driver>.

If i have the 00010 case removed, it synthesises, I really don't know why.

Please help

thank you

 

[Michael Chan]

I'm pretty new to VHDL, but I think your code might work if you give IRDY a
default value:

out_logic: process(current_state)
begin
IRDY <= 'Z';
case
...
end

If a value for IRDY is not specified for all cases, you get a latch, which
doesn't make a lot of sense for 'Z'.

Cheers,

Michael.

 

[Michael]

Thanks for the reply.
I got a question, but doesn't the others statement handle the default value?

thanks

 

[Marc Guardiani]

Michael,
Yes it does, but you're not setting it there. Try adding it and see if
that fixes your problem. BTW, which version of the Xilinx software are
you using?
Marc

 

[Michael]

it's 4.2WP3.x

thanks

Michael,
Yes it does, but you're not setting it there. Try adding it and see if
that fixes your problem. BTW, which version of the Xilinx software are
you using?
Marc

 

[Charles M. Elias]

Michael,
Yes it does, but you're not setting it there. Try adding it and see if
that fixes your problem. BTW, which version of the Xilinx software are
you using?
Marc

It looks as though IRDY never has a value assigned other than 'Z'.
Surely in some case it will have a value of '0' or '1'; otherwise it
is not of much use.

Charles