trouble connecting an out std_logic_vector port to aggregate of signals

Discussion in 'VHDL' started by ihk, Sep 1, 2011.

  1. ihk

    ihk Guest

    Hello,

    Can a VHDL guru help me explaining why for a component defined like
    this

    component nios is
    port (
    pio_in : in std_logic_vector(15 downto 0),
    pio_out : out std_logic_vector(7 downto 0)
    );

    I can do the following assignment:

    nios_1 : nios
    port map (
    pio_in => (
    0 => pll_locked,
    1 => pll_clkswitch,
    others => '0')
    );

    but the following gives syntax error (in Altera Quartus)

    nios_1 : nios
    port map (
    pio_out => (
    0 => led1,
    1 => led2,
    others => open)
    );

    The only way I can make this works is if I do the assignment to
    pio_out like this:
    nios_1 : nios
    port map (
    pio_out(0) => led1,
    pio_out(1) => led2
    );


    Thanks and best regards,
    Ivo
     
    ihk, Sep 1, 2011
    #1
    1. Advertising

  2. ihk

    Pontus Guest

    Not beeing a guru, I should perhaps not attempt an answer...
    (Gurus usually have several limo's, I don't)

    I have been bitten by similar issues before, portmaps
    where parts of a vector should connect, others stay open, etc.

    I think this is an effect of the language trying to limit
    the missuses rather than to allow non-precise statements
    to be accepted. Or perhaps it's some vendors non-compliance
    to the standard.

    Your solution seems pretty clean and expressive, your
    problem was probably getting the compiler to accept the code.

    When I struggled with this, I got some informative compile
    errors from the simulator (modelsim or riviera, can't remember witch).

    HTH -- Pontus

    On 1 Sep, 10:48, ihk <> wrote:
    > Hello,
    >
    > Can a VHDL guru help me explaining why for a component defined like
    > this
    >
    > component nios is
    >    port (
    >        pio_in   : in  std_logic_vector(15 downto 0),
    >        pio_out : out std_logic_vector(7 downto 0)
    > );
    >
    > I can do the following assignment:
    >
    > nios_1 : nios
    >    port map (
    >        pio_in   => (
    >                 0           => pll_locked,
    >                 1           => pll_clkswitch,
    >                 others      => '0')
    >   );
    >
    > but the following gives syntax error (in Altera Quartus)
    >
    > nios_1 : nios
    >    port map (
    >        pio_out   => (
    >                 0           => led1,
    >                 1           => led2,
    >                 others    => open)
    >   );
    >
    > The only way I can make this works is if I do the assignment to
    > pio_out like this:
    > nios_1 : nios
    >    port map (
    >        pio_out(0)  => led1,
    >        pio_out(1)  => led2
    >   );
    >
    > Thanks and best regards,
    > Ivo
     
    Pontus, Sep 1, 2011
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. =?ISO-8859-15?Q?Fr=E9d=E9ric_Lochon?=

    connecting std_logic inout ports and std_logic_vector inout port

    =?ISO-8859-15?Q?Fr=E9d=E9ric_Lochon?=, Nov 6, 2007, in forum: VHDL
    Replies:
    3
    Views:
    898
  2. Thomas Rouam
    Replies:
    6
    Views:
    1,187
  3. Steven Kauffmann
    Replies:
    21
    Views:
    2,781
    Ponceludon de Malavoy
    Jan 9, 2008
  4. Rain
    Replies:
    4
    Views:
    1,014
    Mike Treseler
    Apr 30, 2008
  5. THurkmans
    Replies:
    14
    Views:
    1,951
    Mike Treseler
    Aug 11, 2009
Loading...

Share This Page