trunc in verilog

Discussion in 'VHDL' started by arti, May 10, 2006.

  1. arti

    arti Guest

    hi

    In vhdl I have function trunc
    how can I use this function in verilog
    exp
    a= trunc(b) ;
    Is it possible code this function use only gates AND and or ?

    regards
    arti
     
    arti, May 10, 2006
    #1
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