truncating std_logic_vector multiplication result question

Discussion in 'VHDL' started by vivo_m, Feb 23, 2012.

  1. vivo_m

    vivo_m

    Joined:
    Feb 23, 2012
    Messages:
    3
    Hi,
    I want to multiply two std_logic_vector(7 downto 0),but i want the result to be std_logic_vector(7 downto 0) not std_logic_vector(15 downto 0)..
    is there any idea how can i do this??
     
    vivo_m, Feb 23, 2012
    #1
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  2. vivo_m

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    I think you can simply have,
    Code:
    variable x, y : unsigned(7 downto 0);
    variable z : unsigned(7 downto 0);
    
    z := x * y; -- drops 8 most significant bits
     
    joris, Feb 25, 2012
    #2
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