truncating std_logic_vector multiplication result question

[vivo_m]

Hi,
I want to multiply two std_logic_vector(7 downto 0),but i want the result to be std_logic_vector(7 downto 0) not std_logic_vector(15 downto 0)..
is there any idea how can i do this??

 

[joris]

I think you can simply have,

variable x, y : unsigned(7 downto 0);
variable z : unsigned(7 downto 0);

z := x * y; -- drops 8 most significant bits