I started to write a ttl library but its really hard work.
Are there any good ones out there?
(without after, as they should synticise)
Sounds easy but exceedingly tedious, to me.
Why bother? What's the point? Just do the parts that
you need for your legacy netlist.
The easy stuff (combinational gates with small numbers
of inputs) maps directly on to VHDL operators and
expressions.
More complicated combinational functions, such as
parity generators and special decoders, can easily
be re-coded as VHDL functions, which makes them a whole
lot more flexible and easier to use than they would be
if you packaged them as components.
Most of the synchronous blocks, such as the neat
multiplexer/flipflop combinations (74xx239???), are
just a pale shadow of stuff that you would want to
code in a VHDL clocked process; packaging them as
components will horribly distort your synthesisable
coding style.
Buffers and other bus-interface blocks such as
'245, '543 are unlikely to fit well with FPGA/ASIC
design methodologies because they use multi-drop
interconnect (to reduce package pin count) and
latches (to save logic). Steer clear of these, and
use a more appropriate interconnect scheme.
I have a cartload of 74F devices in my workshop.
It's hard persuading myself that I should get rid
of them, but I'm perfectly sure that I will
never use them again. My guess is that you are a
lot younger than I am; your sentimental attachment
to TTL logic should be much weaker than mine.
Enjoy the 21st century!!!
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
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